A high-frequency circuit includes a first electric conductor layer, a first dielectric layer, a circuit layer, a second dielectric layer, a second electric conductor layer arranged in this order, and the circuit layer includes a ground pattern and a transmission line of a high-frequency signal. An electromagnetic wave shield is disposed around the transmission line. The electromagnetic wave shield includes a ground electric conductor on inner surfaces of a plurality of holes extending through the first dielectric layer, the ground pattern, the second dielectric layer, the first electric conductor layer, and the second electric conductor layer. The plurality of holes are a plurality of elongated holes provided at an interval in a direction in which the transmission line is surrounded. In each of the plurality of elongated holes, a longitudinal dimension in the direction in which the transmission line is surrounded is larger than a width dimension.

The invention discloses a circuit board enhancing structure and a manufacture method thereof. The method includes the following steps: providing a substrate; forming a first circuit on the substrate; forming a first dielectric layer enclosing the first circuit on the substrate; forming a first opening on the first dielectric layer; forming a first pattern photoresist layer on the first dielectric layer to divide a surface of the first dielectric layer as a first structure enhancing area and a second circuit area, wherein the first opening is disposed in the first structure enhancing area; forming a second circuit in the second circuit area and a first enhancing structure in the first opening, wherein the first enhancing structure protrudes from the first opening; removing the first pattern photoresist layer; and forming a second dielectric layer enclosing the second circuit and the first enhancing structure on the first dielectric layer.

A device includes a porous substrate that include a plurality of pores and a plurality of nanodevices dispersed in at least a portion of the plurality of pores. Each of the plurality of nanodevices includes a magnetic nanowire and a solder nanoparticle. The magnetic nanowires are configured to generate heat in response to an alternating magnetic field. The solder nanoparticles are configured to receive a portion of the heat and reflow to connect to one or more devices or surfaces.

A component carrier with a stack including an electrically insulating layer structure and an electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm. A demarcation surface of the plating layer in the blind hole and facing away from the stack extends laterally outwardly from the bottom of the blind hole towards a lateral indentation and extends laterally inwardly from the indentation up to an outer end of the blind hole. An electrically conductive structure fills at least part of a volume between the plating layer and an exterior of the blind hole.

A component carrier with an asymmetric build-up, which includes (a) a core; (b) a first stack at a first main surface of the core, the first stack having at least one first electrically conductive layer structure and a plurality of first electrically insulating layer structures; and (c) a second stack at a second main surface of the core, the second stack having at least one second electrically conductive layer structure and a plurality of second electrically insulating layer structures. At least two of the second electrically insulating layer structures are in direct contact with each other and each one of these electrically insulating layer structures has a smaller thickness than and/or includes a different material property than one of the first electrically insulating layer structures. Further described are methods for designing and manufacturing such an asymmetric component carrier.

Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

A method for manufacturing a circuit board is disclosed. An inner wiring base board with a first opening is provided. A base board is fixed in the first opening, and a first wiring base board and a second wiring base board are pressed on opposite surfaces of the inner wiring base board. The base board is made of ceramic and has a high light reflectivity of 92% to 97%. A first conductor layer and a second conductor layer are formed on opposite surfaces of the laminated structure. The first conductor layer includes a plurality of connecting pads on the base board. A solder mask is formed on an outer side of the first conductor layer, the solder mask has a high light reflectivity of 92% to 95%, and the base board is exposed outside the solder mask.

A wiring substrate includes a first insulating layer with a first opening, a second insulating layer with a second opening, a high-frequency wiring layer, a first wiring layer, a second wiring layer, and a plurality of conductive pillars. The high-frequency wiring layer including a high-frequency trace is sandwiched between the first insulating layer and the second insulating layer. The first opening and the second opening expose two sides of the high-frequency trace respectively. The high-frequency trace has a smooth surface which is not covered by the first insulating layer and the second insulating layer and has the roughness ranging between 0.1 and 2 μm. The first insulating layer and the second insulating layer are all located between the first wiring layer and the second wiring layer. The conductive pillars are disposed in the second insulating layer and connected to the high-frequency trace.

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

A printed circuit board includes: a first insulating layer; a first metal layer disposed on one surface of the first insulating layer; a second metal layer disposed on the other surface facing the one surface of the first insulating layer; a via penetrating through the first insulating layer to connect the first and second metal layers to each other; and a heterogeneous metal region disposed in at least one of an area in which the via is adjacent to the first insulating layer and an area in which the via is adjacent to the first metal layer, and including a material different from that of the via, wherein the heterogeneous metal region includes at least one of nickel (Ni), silicon (Si), and titanium (Ti).