A multilayer substrate comprises: a stack having a plurality of insulating base materials; a first component arranged within the stack at a first level in a thickness direction of the stack; a second component arranged within the stack at a second level different from the first level and arranged so that, in a plan view, at least a portion of the second component overlaps with a portion of the first component; and a supplementary member arranged to at least partly exist in a range, in a thickness direction, as high as or higher than a lower end of the second component and as high as or lower than an upper end of the second component, and in a plan view, within a region of a projected area of the first component not overlapped with the second component, the supplementary member having a rigidness higher than the insulating base materials.

The present disclosure relates to a tunable slow-wave transmission line. The tunable slow-wave transmission line is formed in a multi-layer substrate and includes an undulating signal path. The undulating signal path includes at least two loop structures, wherein each loop structure includes at least two via structures connected by at least one intra-loop trace. The undulating signal path further includes at least one inter-loop trace connecting the at least two loop structures. The tunable slow-wave transmission line includes a first ground structure disposed along the undulating signal path. Further, the tunable slow-wave transmission line includes one or more circuits that may alter a signal transmitted in the tunable slow-wave transmission line so as to tune a frequency of the signal.

The present disclosure relates to a slow-wave transmission line for transmitting slow-wave signals with reduced loss. In this regard, the slow-wave transmission line is formed in a multi-layer substrate and includes an undulating signal path. The undulating signal path includes at least two loop structures, wherein each loop structure includes at least two via structures connected by at least one intra-loop trace. The undulating signal path further includes at least one inter-loop trace connecting the at least two loop structures. Additionally, the slow-wave transmission line includes a first ground structure disposed along the undulating signal path. In this manner, a loop inductance is formed by each of the at least two loop structures, while a first distributed capacitance is formed between the undulating signal path and the ground structure.

A method reduces an area of a mounting electrode provided on a first surface of a multilayer body and connected to a specific component is reduced and decreases a pitch between mounting electrodes. A plating film is formed on the mounting electrodes with the reduced area. The mounting electrodes for connection to specific components are defined by first end surfaces of first via conductors, and hence, the areas of the mounting electrodes are significantly reduced, and the pitch between the mounting electrodes is significantly decreased. Also, the mounting electrodes defined by the first end surfaces of the first via conductors are connected to plane electrodes at end surfaces of second via conductors exposed from a surface of the multilayer body with internal wiring electrodes interposed therebetween. Thus, a plating film is able to be reliably provided on the mounting electrodes.

A multi-layer printed circuit board (PCB) includes a laminate between a PCB heating core and a PCB signal core. The PCB heating core includes an electrically conductive resistive heating element upon a first core substrate. During a lamination cure PCB fabrication stage, a platen contacts the PCB and a power supply is electrically connected to the resistive heating element. The laminate is cured with heat transferred by the platen and heat from the resistive heating element. The PCB heating core may be located within an inner layer of the multi-layer PCB to normalize a thermal gradient across the multi-layer PCB that may otherwise occur during the laminate cure fabrication stage. As a result of the normalized thermal gradient, the degree of laminate cure and material characteristics of the cured laminate material are more consistent throughout the multi-layer PCB thickness.

A stacked body includes a first resin layer including a thermoplastic first resin as a main material, a pattern including a conductor layer on one principal surface of the first resin layer, and a second resin layer including a thermoplastic second resin as a main material. The first resin layer is softer than the second resin layer. The first resin layer has a lower dielectric constant than the second resin layer. A pattern including the conductor layer is at least partially embedded in the first resin layer, and includes a portion in contact with the first resin layer along a layer direction (X-Y plane) of the first resin layer and a portion in contact with the first resin layer along a stacking direction (X-Z plane) of the first resin layer, the second resin layer, and the pattern including the conductor layer.

A semiconductor integrated circuit device (101) includes a component built-in board (21) in which at least a first core layer (Co21) on which a first electronic component (C21) is mounted, a second core layer (Co22) on which a second electronic component (C22) is mounted, an adhesive layer (Ad21) arranged between the first core layer (Co21) and the second core layer (Co22), and wiring layers (L21-L28) are stacked; a third electronic component (SoC) mounted in a first core layer (Co21) side of the component built-in board (21) and electrically connected to at least one of the first and second electronic components (C21, C22) through the wiring layers (L21 to L28); and an external connection terminal (BE) formed in a second core layer (Co22) side of the component built-in board (21) and electrically connected to at least one of the first and second electronic components (C21, C22).

A printed circuit board includes a printed wiring board including an insulative substrate having a first surface and a second surface opposite to the first surface, and wiring provided on the second surface of the insulative substrate to face the through-holes. The insulative substrate has flexibility and through-holes passing through the insulative substrate from the first surface to the second surface. A semiconductor element is mounted on the first surface of the insulative substrate of the printed wiring board and has element terminals interposed between the printed wiring board and the semiconductor element. Conductive members filled in the through-holes connect the element terminals and the wiring. The insulative substrate has elasticity in which an elongation percentage of the insulative substrate is 20% or more. The wiring is formed from a conductive polymer or an elastic conductive paste in which conductive particles are mixed into a resin material.

A component carrier with a stack including a first core layer structure and a second core layer structure, and a recess extending completely through the first core layer structure and extending at least partially into the second core layer structure. Each core layer structure has at least one electrically conductive layer structure and at least one electrically insulating layer structure. The core layer structures are stacked with one on top of the other in a stacking direction.

An inductor component includes first and second inductor wiring lines, a first vertical wiring line, a second vertical wiring line, and a third vertical wiring line, wherein the first vertical wiring line and the second vertical wiring line are connected to the first end portion and the second end portion of the first inductor wiring line, respectively, and the third vertical wiring line and the second vertical wiring line are connected to the first end portion and the second end portion of the second inductor wiring line, respectively.