An electrical conductor includes a substrate; and a first conductive layer disposed on the substrate and including a plurality of metal oxide nanosheets, wherein adjacent metal oxide nanosheets of the plurality of metal oxide nanosheets contact to provide an electrically conductive path between the contacting metal oxide nanosheets, wherein the plurality of metal oxide nanosheets include an oxide of Re, V, Os, Ru, Ta, Ir, Nb, W, Ga, Mo, In, Cr, Rh, Mn, Co, Fe, or a combination thereof, and wherein the metal oxide nanosheets of the plurality of metal oxide nanosheets have an average lateral dimension of greater than or equal to about 1.1 micrometers. Also an electronic device including the electrical conductor, and a method of preparing the electrical conductor.

A circuit board is obtained by providing a wiring pattern on an insulating board. The circuit board includes a first region and a second region. In the first region, a first wiring pattern is provided on which a first surface treatment is applied. In the second region, a second wiring pattern is provided on which a second surface treatment having a cutting fluid resistance and/or a humidity resistance lower than the first surface treatment is applied.

The present invention provides a photosensitive resin composition with which a dry resist film can be obtained, the dry resist film exhibiting excellent storage stability and migration resistance in thickness direction thereof. This photosensitive resin composition comprises: a photosensitive prepolymer having a carboxyl group and an ethylenically unsaturated group; a photopolymerization initiator; and a thermosetting agent. The thermosetting agent is a polycarbodiimide compound represented by formula (1), in which a carbodiimide group is protected by an amino group that dissociates at temperatures of 80 C. or greater. The polycarbodiimide compound has a weight average molecular weight of 300-3000, and a carbodiimide equivalent weight of 150-600. In formula (1), R.sup.1, R.sup.2, X.sup.1, X.sup.2, and n are as defined in the description.

A printed circuit board includes a spread weave of fibers having a first direction and a second direction with corresponding fibers spread more in the first direction than the second direction; and one or more pairs of traces on the spread weave of fibers, wherein the first direction has less differences in dielectric permittivity seen by each trace than the second direction, wherein the one or more pairs of traces are routed according to a routing design that includes one or more fixed regions on the spread weave of fibers, where routing of traces therein is restricted to linear, non-angled routed in the first direction.

Described are various configurations of high-speed via structures. Various embodiments can reduce or entirely eliminate insertion loss in high-speed signal processing environments by using impedance compensation structures that decrease a mismatch in components of a circuit. An impedance compensation structure can include a metallic structure placed near a via to lower an impedance difference between the via and a conductive pathway connected to the via.

A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.

Vertical launch impedance matched through-hole vias to ensure proper impedance matching is maintained after a printed circuit board connector is attached to a printed circuit board. A conductive via having a center aperture and a via body having a slot adjacent either the via top surface and/or via bottom surface, and a dielectric component insertable within the via center aperture, and having a slot aligned with the conductive via body slot. The dielectric component having a center aperture with a conductive member in electrical communication with a PCB signal trace without contact to the conductive via. A printed circuit board connector having a center signal pin with a slotted dielectric component attached thereto, or a slotted dielectric component in conjunction with a slotted, conductive via body attached thereto.

The present invention aims to provide a printed wiring board in which an increase in electrical resistance between a ground circuit and a reinforcement member of the printed wiring board is inhibited. The printed wiring board of the present invention includes: a substrate film including a base film and a printed circuit including a ground circuit; an adhesive layer formed on the substrate film; and a conductive reinforcement member formed on the adhesive layer, wherein the adhesive layer contains conductive particles and an adhesive resin, the conductive particles are at least one selected from the group consisting of first conductive particles each including a non-conductive core particle and a first low-melting-point metal layer formed on the non-conductive core particle, intrinsically conductive second conductive particles, and third conductive particles each including a conductive core particle and a first low-melting-point metal layer formed on the conductive core particle; a second low-melting-point metal layer is formed between the substrate film and the adhesive layer, or the substrate film is in direct contact with the adhesive layer; a third low-melting-point metal layer is formed between the adhesive layer and the reinforcement member, or the adhesive layer is in direct contact with the reinforcement member; the printed wiring board includes at least one low-melting-point metal layer selected from the group consisting of the first low-melting-point metal layer, the second low-melting-point metal layer, and the third low-melting-point metal layer; and the ground circuit is electrically connected to the reinforcement member via at least one low-melting-point metal layer selected from the group consisting of the first low-melting-point metal layer, the second low-melting-point metal layer, and the third low-melting-point metal layer.

Provided is an electronic apparatus capable of improving time margin. The electronic apparatus includes: a base substrate including a substrate base including a plurality of layers and a plurality of wiring layers between the layers; a controller chip and at least one memory semiconductor chip mounted on the base substrate; a signal line disposed in one of the wiring layers and connecting the controller chip to the at least one memory semiconductor chip; and a pair of open stubs disposed in another wiring layer, connected to both ends of the signal line, and extending to face each other with a gap.

Described are various configurations of high-speed via structures. Various embodiments can reduce or entirely eliminate insertion loss in high-speed signal processing environments by using impedance compensation structures that decrease a mismatch in components of a circuit. An impedance compensation structure can include a metallic structure placed near a via to lower an impedance difference between the via and a conductive pathway connected to the via.