A composite electronic component includes a composite body including a multilayer ceramic capacitor and a ceramic chip coupled to each other. The multilayer ceramic capacitor includes a first ceramic body and first and second external electrodes, and the ceramic chip is disposed below the multilayer ceramic capacitor and includes a second ceramic body having first and second terminal electrodes. The multilayer ceramic capacitor and the ceramic chip are coupled by solder disposed between the first and second external electrodes and the first and second terminal electrodes, and each angle (θ) defined by inner side surfaces of the solder, respectively disposed on inner ends of bent portions of the first and second terminal electrodes disposed on an upper surface of the second ceramic body, and an upper plane of the second ceramic body of the ceramic chip satisfies 45 degrees or less.

A multilayer electronic component includes a multilayer capacitor including a capacitor body in which internal electrodes are stacked to be parallel with respect to a mounting surface and external electrodes disposed on opposing end surfaces of the capacitor body, respectively, and a metal frame having a solder pocket and including a vertical portion, an upper horizontal portion extending from an upper end of the vertical portion, and a lower horizontal portion extending from a lower end of the vertical portion, the upper horizontal portion connected to an upper band portion of each of the external electrodes. 0.1≤G/CT≤0.7 is satisfied, in which CT is a height of the vertical portion and G is a distance between the lower band portion of each of the external electrodes and a lower end of the metal frame.

A composite electronic component includes a multilayer ceramic capacitor including a ceramic body configured by stacking a plurality of dielectric layers and configured by stacking a plurality of internal electrodes facing each other with the dielectric layer interposed therebetween and first and second external electrodes disposed on opposing end portions of the ceramic body, and a pair of substrates spaced apart from a lower portion of the multilayer ceramic capacitor and each including, on opposing end portions, first terminal electrodes connected to the first external electrode and second terminal electrodes connected to the second external electrode.

A printed wiring board includes a substrate, a contact member arranged in contact with the substrate, and a wear resistant member fixed at least in an area on the substrate that comes in contact with the contact member, the wear resistant member having a wear resistance higher than that of the substrate.

Each of a supporting-terminal-equipped capacitor chip and a mounted structure thereof includes a capacitor chip and first and second supporting terminals that each have electric conductivity. A maximum diameter size of the first supporting terminal when viewed in an axial direction is larger than a maximum length size of a portion of a first outer electrode on a second main surface in a length direction. A maximum diameter size of the second supporting terminal when viewed in the axial direction is larger than a maximum length size of a portion of a second outer electrode on the second main surface in the length direction.

A supporting-terminal-equipped capacitor chip includes a capacitor chip, and first and second supporting terminals that are electrically conductive and hold the capacitor chip therebetween. A portion of the capacitor chip other than a first connection portion and the first supporting terminal are separated from each other. A portion of the capacitor chip other than a second connection portion and the second supporting terminal are separated from each other. The first connection portion is located on the first main surface adjacent to a first end surface. The second connection portion is located on the first main surface adjacent to a second end surface.

A mounted structure of a supporting-terminal-equipped capacitor chip includes first and second supporting terminals. The first supporting terminal includes a first helical electrically conductive portion extending in a first axial direction along a main surface. The second supporting terminal includes a second helical electrically conductive portion extending in a second axial direction along the main surface. The first helical electrically conductive portion is electrically connected to a first outer electrode at an outer peripheral side surface of the first helical electrically conductive portion. The second helical electrically conductive portion is electrically connected to a second outer electrode at an outer peripheral side surface of the second helical electrically conductive portion.

Relatively low noise capacitors are provided for surface mounted applications. Electro-mechanical vibrations generate audible noise, which are otherwise relatively reduced through modifications to MLCC device structures, and/or their mounting interfaces on substrates such as printed circuit boards (PCBs). Different embodiments variously make use of flexible termination compliance so that surface mounting has reduced amplitude vibrations transmitted to the PCB. In other instances, side terminal and transposer embodiments effectively reduce the size of the mounting pads relative to the case of the capacitor, or a molded enclosure provides standoff, termination compliance and clamping of vibrations.

According to one aspect of the present invention, a lead-free solder alloy includes 2% by mass or more and 3.1% by mass or less of Ag, more than 0% by mass and 1% by mass or less of Cu, 1% by mass or more and 5% by mass or less of Sb, 3.1% by mass or more and 4.5% by mass or less of Bi, 0.01% by mass or more and 0.25% by mass or less of Ni, and Sn.

A multilayer electronic component includes: a capacitor body having first to sixth surfaces, and including first and second internal; first and second external electrodes including first and second connection portions and first and second band portions; and a connection terminal including first and second land portions disposed on the first and second band portions, respectively, and having first and second cut-out portions, respectively. First and second solder accommodating portions are provided by the first and second cut-out portions in lower portions of the first and second band portions, respectively, and, 0.2SA1/BW10.5 and 0.2SA2/BW20.5 which in BW1 is an area of the first band portion, SA1 is an area of the first solder accommodating portion, BW2 is an area of the second band portion, and SA2 is an area of the second solder accommodating portion.