A conductive network fabrication process is provided and includes filling a hole formed in a substrate with dielectric material, laminating films of the dielectric material on either side of the substrate, opening a through-hole through the dielectric material at the hole, depositing a conformal coating of dielectric material onto an interior surface of the through-hole and executing seed layer metallization onto the conformal coating in the through-hole to form a seed layer extending continuously along an entire length of the through-hole.

A high-frequency module (1) includes a component (3a) mounted on an upper surface (2a) of a substrate (2), a second sealing resin layer (4) stacked on the upper surface (2a) of the substrate (2), a component (3b) mounted on a lower surface (2b) of the substrate (2), a first sealing resin layer (5) stacked on the lower surface (2b) of the substrate (2), and a first terminal assembly (6) and a second terminal assembly (7) that are mounted on the lower surface (2b) of the substrate (2). The first terminal assembly (6) is mounted on a four-corner portion of the substrate (2) and includes a connection conductor (6a) thicker than a connection conductor (7a) of the second terminal assembly (7).

A single-layer redistribution plate functioning as a space translator between a device under testing (“DUT”) and a testing PCB may comprise a hard ceramic plate. A DUT side of the plate may have pads configured to interface with a device under testing. Both sides of the plate may comprise traces, vias, and pads to fan out the DUT pad pattern so that the plate side opposite the DUT side has spatially translated pads configured to interface with the pads on a testing PCB. Fabricating a redistribution plate may comprise calibrating and aligning, laser milling vias, laser milling trenches and pads, copper plating, grinding and polishing, removing residual copper, and coating the copper surfaces.

A conductive network fabrication process is provided and includes filling a hole formed in a substrate with dielectric material, laminating films of the dielectric material on either side of the substrate, opening a through-hole through the dielectric material at the hole, depositing a conformal coating of dielectric material onto an interior surface of the through-hole and executing seed layer metallization onto the conformal coating in the through-hole to form a seed layer extending continuously along an entire length of the through-hole.

A printed circuit board (PCB) having an engineered thermal path and a method of manufacturing are disclosed herein. In one aspect, the PCB includes complementary cavities formed on opposite sides of the PCB. The complementary cavities are in a thermal communication and/or an electrical communication to form the engineered thermal path and each cavity is filled with a thermally conductive material to provide a thermal pathway for circuits and components of the PCB. The method of manufacturing may further include drilling and/or milling each cavity, panel plating the cavities and filling the cavities with a suitable filling material.

A printed circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a pad disposed on the first insulating layer and exposed through the cavity; wherein the second insulating layer includes a first portion disposed on an upper surface of the first insulating layer in a region where the cavity is formed; and a second portion other than the first portion, and wherein a thickness of the first portion is smaller than a thickness of the second portion.

A method for repairing a fine line is provided. Nano metal particles are filled in a defect of a circuit board. The nano metal particles in the defect are irradiated by a laser, or heated, such that the nano metal particles in the defect are metallurgically bonded to an original line of the circuit board. A surface of the circuit board is cleaned to remove residual nano metal particles on parts of the circuit board where metallurgical bonding is not performed, thereby completing line repairing of the circuit board.

An interconnect substrate includes a lower-modulus buffer material disposed around a thermally conductive base and a higher-modulus crack stopper disposed over the buffer material. By the difference of the elastic modulus between the crack stopper and the buffer material, thermo-mechanical induced stress can be absorbed in the buffer material, and crack propagation would be arrested by the crack stopper to ensure reliability of a routing trace which is deposited on the crack stopper and electrically coupled to vertical connecting elements in the buffer material. Further, the crack stopper can have low dissipation factor to ensure a lower rate of energy loss which is beneficial to high frequency applications.

A substrate having an electronic component embedded therein includes a core structure including a first insulating body and a plurality of core wiring layers disposed on or in the first insulating body, and having a cavity penetrating at least a portion of the first insulating body in a thickness direction of the substrate and including a stopper layer as a bottom surface of the cavity, and an electronic component disposed in the cavity and attached to the stopper layer, and a surface of the stopper layer connected to the electronic component has a composite including at least two among a metal material, an inorganic particle, a filler, and an insulating resin.

A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.