A method for producing a metal foil comprising depositing metal onto an oxidizable substrate to form a metal film on the substrate; oxidizing the substrate at an interface between the metal film and the substrate; and removing the metal film from the substrate to yield a metal foil. A method for forming a thin metal film comprising pre-polarizing a single-crystal Si substrate by application of a potential which is negative of a potential at which Si oxidizes, which pre-polarization occurs in the presence of metal ions to form metal growth nucleation sites on the substrate, followed by application of a potential at which both oxidation of Si and electrodeposition of the metal occur to grow the metal film and oxidize the Si to SiOx, which potential is more positive than the potential applied in the pre-polarization step.

Proposed is a multilayer wiring substrate having excellent joining strength, a method of manufacturing the multilayer wiring substrate, and a probe card having the multilayer wiring substrate.

A substrate (1, 10) for electrical circuits, comprising at least one metal layer (2,3, 14) and a paper ceramic layer (11), which is joined face to face with the at least one metal layer (2,3, 14) and has a top side and bottom side (11a, 11b), wherein the paper ceramic layer (11) has a large number of cavities in the form of pores. Especially advantageously, the at least one metal layer (2, 3, 14) is connected to the paper ceramic layer (11) by means of at least one glue layer (6, 6a, 6b), which is produced by applying at least one glue (6a, 6a, 6b, 6b) to the metal layer (2,3, 14) and/or to the paper ceramic layer (11), wherein the cavities in the form of pores in the paper ceramic layer (11) are filled at least at the surface by means of the applied glue (6a, 6a, 6b,6b).

A semiconductor device and a method for producing a carrier element suitable for a semiconductor device are disclosed. In an embodiment a semiconductor device includes a carrier element including a carrier layer having a first depression extending from a first main surface of the carrier layer in a direction of a second main surface of the carrier layer opposite the first main surface and a metal substrate and an electrically insulating layer on at least a portion of the metal substrate, a first electrically conductive filling component arranged in the first depression in a form-fitting manner, the electrically insulating layer being arranged between the metal substrate and the first filling component and a semiconductor chip arranged on the carrier element, wherein the electrically insulating layer is an anodization layer.

A wiring circuit board includes a metal supporting board, first and second metal thin films, an insulating layer, and a conductive layer, where the resistance between the conductive layer and metal supporting board are lowered. The first metal thin film is disposed on one surface of the metal supporting board in the thickness direction, with the insulating layer having a through hole. The second metal thin film is disposed on one surface of the insulating layer in the thickness direction with the conductive layer disposed thereon. In the through hole, the first and second metal thin films, whose surfaces contact, are disposed between the metal supporting board and the conductive layer, and the other surface of the first metal thin film is in contact with the one surface of the metal supporting board. The other surface of the second metal thin film is in contact with the conductive layer.

The invention relates to a substrate (1) for electrical circuits comprising at least one first composite layer (2) which is produced by means of roll cladding and, after said roll cladding, has at least one copper layer (3) and an aluminium layer (4) attached thereon, wherein at least the surface side of the aluminium layer (4) facing away from the copper layer (3) is anodized for the generation of an anodic or insulating layer (5) made of aluminium oxide, and wherein the anodic or insulating layer (5) made of aluminium oxide is connected to a metal layer (7) or at least one second composite layer (2) or at least one paper-ceramic layer (11) via at least one adhesive layer (6, 6).

A method for making conformal non-planar multi-layer circuitry is described. The method can include providing a substrate having a non-planar surface and depositing a first conformal dielectric layer on the substrate, the first conformal dielectric layer conforming to the non-planar surface of the substrate and having a non-planar surface. The method can also include applying a first conformal circuitry layer on the first conformal dielectric layer. The method can include depositing a second conformal dielectric layer on the first conformal circuitry layer, the second conformal dielectric layer conforming to a non-planar surface of the first conformal circuitry layer, and applying a second conformal circuitry layer on the second conformal dielectric layer. Successive layers can be sequentially deposited.

An electrical contact pin is intended for pressing into a hole which is provided in a circuit carrier board and has a circumferential wall with a metallized surface. The contact pin consists mainly of copper or of a copper alloy and is surrounded by a layer which includes tin at least in a part region which is to be pressed into the hole. The layer, which includes tin, forms the surface of the contact pin and includes substantially only tin and tin oxide, wherein the tin oxide is formed by way of electrolytic oxidation and the concentration thereof is greatest on the surface of the layer.

The present invention relates to a process for producing one or more electrical contacts on a component, comprising (a) applying one or more coatings on the component, where at least one of the coatings is a coating of an electrically conductive material, (b) applying a self-passivating metal or semiconductor and/or a dielectric material on the coated component, (c) structuring the passivating coating by laser treatment or etching, (d) contacting the structured coating with an electroplating bath, (e) etching the regions not covered with the galvanically deposited metal.

A method for making conformal non-planar multi-layer circuitry is described. The method can include providing a substrate having a non-planar surface and depositing a first conformal dielectric layer on the substrate, the first conformal dielectric layer conforming to the non-planar surface of the substrate and having a non-planar surface. The method can also include applying a first conformal circuitry layer on the first conformal dielectric layer. The method can include depositing a second conformal dielectric layer on the first conformal circuitry layer, the second conformal dielectric layer conforming to a non-planar surface of the first conformal circuitry layer, and applying a second conformal circuitry layer on the second conformal dielectric layer. Successive layers can be sequentially deposited. Microvias may provide electrical connections between circuit layers.