Patent classifications
H05K2203/0338
PACKAGING SUBSTRATE FOR SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND METHOD
A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.
Portable electronic device contact puck alignment
A device interconnection system uses an indexed carrier to locate an array of contacts on an array of solder pads on a printed circuit board. In an embodiment, the PCB is indexed to a device housing in the same manner that it is indexed to the carrier, allowing the array of contacts to match and protrude through an array of holes in the housing. In a further embodiment, the housing is substantially metallic, and the array of holes in the housing are located in an insulating plate formed in the housing.
Solder bump forming member, method for manufacturing solder bump forming member, and method for manufacturing electrode substrate provided with solder bump
A solder bump forming member including: a base substrate having a plurality of recesses; and solder particles in the recesses, in which the solder particle has an average particle diameter of 1 to 35 m and a C.V. value of 20% or less, and a part of the solder particle projects from the recess, or in cross-sectional view, when a depth of the recess is designated as H.sub.1, and a height of the solder particle is designated as H.sub.2, H.sub.1<H.sub.2 is established.
Nanostructured Copper for Electromagnetic Interference Shielding and Method for same
A method of applying an electromagnetic interference (EMI) shield to a substrate includes depositing a layer of ink onto the substrate. The ink contains copper (Cu) nanoplates and a solvent. The solvent is evaporated from the deposited layer, and the deposited layer is sintered to form an EMI shield. In some embodiments, the ink also includes copper nanoparticles and/or copper nanowires. In another aspect, an EMI shield includes a layer of sintered copper nanoplates, and optionally, copper nanoparticles and/or copper nanowires.