The invention relates to a thermoplastic composition comprising a thermoplastic polymer, a laser direct structuring (LDS) additive and a LDS synergist, wherein the composition comprises: (A) a thermoplastic polymer; (B) a LDS additive comprising a tin-based metal oxide; and (C) a metal salt of a phosphinic acid or a diphosphinic acid, or any mixtures thereof.

A multilayer circuit board comprises an inner circuit board, a tin layer, at least one outer circuit board, and a solder mask. The inner circuit board comprises at least one first mounting region and at least one second mounting region. The tin layer is formed on a surface of the inner circuit board except the first mounting region connecting the outer circuit board. The outer circuit board comprises at least one first opening to expose the first mounting region and at least one second opening to expose a portion of the tin layer covering the second mounting region. The inner circuit board, the tin layer, and the outer circuit board together form a middle structure. The solder mask covers the middle structure except the portion and the first mounting region. A treatment layer is formed on the first mounting region.

A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.

A carrier plate includes a substrate and at least one conductor track. The conductor track includes a first layer, which is applied directly on the substrate, and a second layer, which is arranged on the first layer. The second layer includes a supply line region and a soldering region. Furthermore, the second layer is completely interrupted between the supply line region and the soldering region. A device can be produced with a carrier plate and an electrical component arranged on the carrier plate.

Embodiments herein relate to creating a high-aspect ratio opening in a package. Embodiments may include applying a first laminate layer on a side of a substrate, applying a seed layer to at least part of the laminate layer, building up one or more copper pads on the seed layer, etching the seed layer to expose a portion of the first laminate layer, applying a second laminate layer to fill in around the sides of one or more copper pads, and removing part of the buildup copper pads. Other embodiments may be described and/or claimed.

Provided is an electronic component including a base body, a first internal element, a first external electrode, and a second external electrode. The first external electrode has a first outer metal layer and a first inner metal layer that is provided between the first outer metal layer and the first internal element, the second external electrode has a second outer metal layer and a second inner metal layer that is provided between the second outer metal layer and the first internal element, and the first inner metal layer has a lower laser absorption rate than any of the first outer metal layer and the second outer metal layer, and the second inner metal layer has a lower laser absorption rate than any of the first outer metal layer and the second outer metal layer.

A wiring substrate includes a core substrate including a glass substrate and a through-hole conductor formed in the glass substrate, a resin insulating layer formed on the core substrate and including resin and inorganic particles, a conductor layer formed on the insulating layer and including a seed layer and an electrolytic plating layer, and a via conductor formed in the insulating layer such that the via conductor is electrically connected to the through-hole conductor formed in the glass substrate and includes the seed layer and electrolytic plating layer extending from the conductor layer. The conductor layer and the via conductor are formed such that the seed layer is formed by sputtering, and the resin insulating layer has an opening in which the via conductor is formed such that the inorganic particles include first particles forming an inner wall surface in the opening and second particles embedded in the insulating layer.

Embodiments herein relate to creating a high-aspect ratio opening in a package. Embodiments may include applying a first laminate layer on a side of a substrate, applying a seed layer to at least part of the laminate layer, building up one or more copper pads on the seed layer, etching the seed layer to expose a portion of the first laminate layer, applying a second laminate layer to fill in around the sides of one or more copper pads, and removing part of the buildup copper pads. Other embodiments may be described and/or claimed.

A manufacturing method for a printed circuit board includes: transferring roughness of a metal film to an insulating layer by laminating the metal film on the insulating layer, the metal film having the roughness formed on one surface thereof and having a discrete metal layer laminated thereon; exposing a surface of the insulating layer, on which the roughness is transferred, by removing the metal film; processing the surface of the insulating layer having the roughness formed thereon with an acidic solution; and forming a circuit pattern on the insulating layer by a plating process.

A method of manufacturing a printed circuit board with embedded electronic components fixed by a solder paste includes: providing a carrier board with a copper foil layer on the carrier board, an insulating layer on the copper foil layer, and an opening on the insulating layer by laser; putting a solder paste into the opening to form a solder paste layer; performing a high-temperature reflow process of the electronic components on the solder paste layer until the solder paste layer is molten; curing the solder paste layer after cooling to fix the components to the center position of the opening; placing the copper foil layer below the electronic components and removing the solder paste layer; and performing copper plating and electroplating processes in an electroplating space to form a plating copper. The cohesion of the molten solder paste pulls the electronic components towards the center to eliminate position offset produced when the electronic components are installed.