An electronic assembly is disclosed that includes a flexible insulating film, a semiconductor component that has a thickness of less than 50 micrometers, a conductive interconnect extending through the flexible insulating film, a second patterned metal wiring film adjacent, and a third patterned metal wiring film. The second patterned metal wiring film is electrically coupled with the third patterned metal wiring film through the conductive interconnect. The semiconductor component is coupled to the first patterned metal wiring film and at least one of the second patterned metal wiring film or the third patterned metal wiring film.

Embodiments herein relate to creating a high-aspect ratio opening in a package. Embodiments may include applying a first laminate layer on a side of a substrate, applying a seed layer to at least part of the laminate layer, building up one or more copper pads on the seed layer, etching the seed layer to expose a portion of the first laminate layer, applying a second laminate layer to fill in around the sides of one or more copper pads, and removing part of the buildup copper pads. Other embodiments may be described and/or claimed.

A method may involve: forming a first bio-compatible layer; forming an etch stop over a portion of the first bio-compatible layer; forming a conductive pattern over the etch stop and the first bio-compatible layer, wherein the conductive pattern defines an antenna, sensor electrodes, electrical contacts, and one or more electrical interconnects; mounting an electronic component to the electrical contacts; forming a second bio-compatible layer over the electronic component, the antenna, the sensor electrodes, the electrical contacts, the one or more electrical interconnects, and the etch stop; and etching, using an etchant, a portion of the second bio-compatible layer to form an opening in the second bio-compatible layer and thereby expose the sensor electrodes, wherein the etch stop inhibits etching of the portion of the first bio-compatible layer by the etchant.

Disclosed are an array substrate and a method for manufacturing the same. The array substrate includes a transmission gate structure having an upper thin film transistor and a lower thin film transistor. An active layer of the lower TFT is the first active layer, and an active layer of the upper TFT is the second active layer. The first active layer and the second active layer are provided on two sides of a source and drain layer, respectively, and share source and drain electrodes. Compared with the prior art, such structure is simpler, and furthermore it facilitates simplification of a manufacturing process of the transmission gate structure and improves a success rate of preparation thereof.

An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.

A wiring substrate includes an insulating layer including a projection and a wiring layer on the projection. The wiring layer includes a first metal layer on an end face of the projection and a second metal layer on the first metal layer. The width of the end face of the projection is different from at least one of the width of the first metal layer and the width of the second metal layer. An inner wall surface and a bottom surface of a depression around the projection are roughened surfaces.

A rigid flex board module includes a rigid flex circuit board and a high-density interconnected circuit board. The rigid flex circuit board includes a flexible circuit board, a first rigid circuit board and a first adhesive layer. The flexible circuit board includes a bending portion and a jointing portion connected to the bending part. The rigid flex circuit board is disposed on the jointing portion to expose the bending portion. The first rigid circuit board electrically connects with the flexible circuit board. The first adhesive layer connects the first rigid circuit board and the jointing portion. The high-density interconnected circuit board is disposed in the first rigid circuit board and is electrically connected to the first rigid circuit board.

A printed circuit board and a method of manufacturing a printed circuit board are provided. The printed circuit board includes an insulating layer, a circuit layer embedded in the insulating layer, a solder resist layer disposed on one surface of the insulating layer, the solder resist layer having a cavity of a through-hole shape to expose a part of the circuit layer from the insulating layer, and a metal post embedded in the solder resist layer and exposed to outside via an opening of the solder resist layer, and the metal post includes a first post metal layer, a post barrier layer, and a second post metal layer disposed in that order.

An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.

An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.