According to an aspect of the disclosure, an example microelectronic device assembly includes a substrate, a microelectronic element electrically connected to the substrate, a stiffener element overlying the substrate, and a heat distribution device overlying the rear surface of the microelectronic element. The stiffener element may extend around the microelectronic element. The stiffener element may include a first material that has a first coefficient of thermal expansion (“CTE”). A surface of the stiffener element may face toward the heat distribution device. The heat distribution device may include a second material that has a second CTE. The first material may be different than the second material. The first CTE of the first material of the stiffener element may be greater than the second CTE of the second material of the heat distribution device.

An electronic device package includes: a substrate including a central region, and a first side region and a second side region at opposite sides of the central region; a first component in the first side region or the second side region, the first component having a first height above a surface of the substrate; a second component in the central region, the second component having a second height above the surface of the substrate that is lower than the first height; a reinforcement member in the central region and overlapping the second component, the reinforcement member having a third height above the surface of the substrate that is lower than the first height and higher than the second height; and an encapsulation member covering the first component and the second component.

A connection structure including: a first circuit member having a plurality of first electrodes; a second circuit member having a plurality of second electrodes; and an intermediate layer having a plurality of bonding portions electrically connecting the first electrodes and the second electrodes, in which at least one of the first electrode and the second electrode that are connected by the bonding portion is a gold electrode, and 90% or more of the plurality of bonding portions include a first region containing a tin-gold alloy and connecting the first electrode and the second electrode and a second region containing bismuth and being in contact with the first region.

Provided are a lead-free and antimony-free solder alloy, a solder ball, and a solder joint that have improved shear strength obtained by grain minuteness at a bonded interface and can suppress fusion failure. The lead-free and antimony-free solder alloy having an alloy composition consisting of, by mass%, 0.1 to 4.5% of Ag, 0.20 to 0.85% of Cu, 0.2 to 5.00% of Bi, 0.005 to 0.09% of Ni, and 0.0005 to 0.0090% of Ge with the balance being Sn, and the alloy composition satisfies the following relations (1) and (2): 0.013 ≤ (Ag + Cu + Ni + Bi) x Ge ≤ 0.027 (1), Sn x Cu x Ni ≤ 5.0 (2). Ag, Cu, Ni, Bi, Ge, and Sn in the relations (1) and (2) each represent the contents (mass%) in the alloy composition.

A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.

A memory module includes a printed circuit board (PCB) including a multi-layer having a wiring structure formed therein. A length of the PCB in a first direction is longer than a length of the PCB in a second direction perpendicular to the first direction. A plurality of memory chips includes a plurality of solder balls. The plurality of memory chips is arranged in a first row and a second row respectively extending in the first direction on the PCB. The plurality of solder balls is continuously arranged in the first direction. The wiring structure alternately zigzag-connects the plurality of memory chips arranged in the first row and the second row.

3D electrical integration is provided by connecting several component carriers to a single substrate using contacts at the edges of the component carriers making contact to a 2D contact array (e.g., a ball grid array or the like) on the substrate. The resulting integration of components on the component carriers is 3D, thereby providing much higher integration density than in 2D approaches.

The invention relates to a solder ball feeding device, comprising a solder ball reservoir for receiving an amount of solder balls and a metering device for dispensing a metered feeding amount of solder balls to a discharge device, wherein the metering device comprises an ultrasound device and a dispensing nozzle with a dispensing cannula, the ultrasound device serving to apply vibrations to the dispensing nozzle, and the solder ball reservoir or the dispensing nozzle of the solder ball reservoir being provided with a pressure connection which serves to introduce a pressurized gas into the solder ball feeding device.

A ball-grid-array component of a ball-grid array assembly is analyzed prior to reflow. A predicted warping pattern of the ball-grid-array component that is likely to occur during reflow is predicted based on the analyzing. A solder ball ball-grid-array defect that could be caused by the predicted warping pattern is predicted. An initial via suction pattern to mitigate the ball-grid-array defect is assigned. A vacuum head is applied to a via in the ball-grid-array assembly. The solder ball is located at the opposite end of the via from the vacuum head. Suction is applied to the via based on the via suction pattern. The suction draws a portion of the solder ball into the via during reflow.

Disclosed is a printed circuit board according to an embodiment. The printed circuit board comprises: a base board; a metal layer, including a pad and a metal line formed in the base board; a solder resist layer that is formed on the base board on which the metal layer is formed and has an opening through which the surface of the metal line is exposed; and an underfill that is formed between the solder resist layer and a semiconductor chip electrically connected to the pad and includes a blocking area formed in the opening.