Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first layer of a package substrate and a conductive trace over the first layer of the package substrate. In an embodiment, the conductive trace comprises a conductive body with a first surface over the first layer of the package substrate, a second surface opposite the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, the second surface has a first roughness and the sidewall surfaces have a second roughness that is less than the first roughness.

A method of manufacturing a printed circuit board includes providing an insulating layer, forming a plating seed layer on the insulating layer, forming a first circuit pattern on the plating seed layer and a second circuit pattern on the first circuit pattern, and forming a top metal layer on the second circuit pattern. The second circuit pattern can be thinner than the first circuit pattern, and the top metal layer can be wider than the second circuit pattern.

A manufacturing method of a circuit board and a stamp are provided. The method includes the following steps. A circuit pattern and a dielectric layer covering the circuit pattern are formed on a dielectric substrate. A conductive via connected to the circuit pattern is formed in the dielectric layer. A photoresist material layer is formed on the dielectric layer. An imprinting process is performed on the photoresist material layer using a stamp to form a patterned photoresist layer, wherein the pressing side of the stamp facing the circuit pattern becomes sticky when subjected to pressure so as to catch photoresist residue from the photoresist material layer in the imprinting process. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed.

A method is described for method for patterning a metal layer interfaced with a transparent conductive film, in which the method comprises contacting a structure through a patterned mask with an etching solution comprising Fe.sup.+3 ions, wherein the structure comprises the metal layer comprising copper, nickel, aluminum or alloys thereof covering at least partially a transparent conductive film with conductive elements comprising silver, to expose a portion of the transparent conductive film. Etching solutions and the etched structures are also described.

The present disclosure relates to a structure and a method for filling a via hole formed in a multilayer printed circuit board, and more particularly, to a structure and a method for filling a via hole formed in a multilayer printed circuit board, the structure and method enabling high-current transmission even in a narrow space in such a way that a via hole formed when a typical multilayer printed circuit board is manufactured is first filled with Cu and Ag plating, and the remaining vacant space is completely filled with a solder cream, thereby increasing the amount of conductors.

A method of masking a feature of a substrate using a fixture includes removably coupling a fixture to a first side of the feature of the substrate, the fixture including walls configured to abut sides of the feature and extend beyond a top surface of the feature when the fixture is removably coupled to the first side. The method further includes applying a masking material to the top surface of the feature. The method further includes removably coupling the fixture to a second side of the feature, the second side opposing the first side, the walls of the fixture configured to abut the sides of the feature and extend beyond a bottom surface of the feature when the fixture is removably coupled to the second side. The method further includes applying the masking material to the bottom surface of the feature while the fixture is removably coupled.

An apparatus for transmitting electrical signals is disclosed. The apparatus includes a substrate and a twisted pair of conductors located on the substrate. The twisted pair of conductors has a first layer comprising conductive material, a second layer comprising nonconductive material, and a third player comprising conductive material. The first layer has a plurality of segments separated by a plurality of gaps. The second layer is positioned in said gaps and electrically insulates a portion of the segments positioned within the gaps. The third layer is positioned over the second layer. The third layer is configured to electrically connects an end of one segment to an end of another segment. The twisted pair of conductors formed by the three dimensional structure comprises two electrically isolated conductors twisted about each other.

A manufacturing method of a circuit board and a stamp are provided. The method includes: forming a circuit pattern and a dielectric layer on a dielectric substrate; forming a conductive via in the dielectric layer; forming a thermal-sensitive adhesive layer on the dielectric layer; forming a photoresist material layer on the thermal-sensitive adhesive layer; imprinting the photoresist material layer using a stamp, wherein a first conductive layer is disposed on the surface of the pressing side of the stamp, a second conductive layer is disposed on the surface of the other portions; applying a current to the stamp; removing the stamp and the photoresist material layer and the thermal-sensitive adhesive layer below the pressing side to form a patterned photoresist layer and thermal-sensitive adhesive layer; forming a patterned metal layer on the region exposed by the patterned photoresist layer; removing the patterned photoresist layer and thermal-sensitive adhesive layer.

A manufacturing method of a circuit board including the following steps is provided. A carrier substrate is provided. A patterned photoresist layer is formed on the carrier substrate. An adhesive layer is formed on the top surface of the patterned photoresist layer. A dielectric substrate is provided. A circuit pattern and a dielectric layer covering the circuit pattern are formed on the dielectric substrate, wherein the dielectric layer has an opening exposing a portion of the circuit pattern. The adhesive layer is adhered to the dielectric layer in a direction that the adhesive layer faces of the dielectric layer. The carrier substrate is removed. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed. The adhesive layer is removed.

To prevent degradation of electrical characteristics caused by a resin filled between electrodes in an ultraviolet light-emitting operation, the present invention provides a base 10 that comprises an insulating base material 11 and two or more metal films 12 and 13 that are formed on one side of the insulating base material 11 and electrically separated from each other. The two or more metal films are formed to include an upper surface and a side wall surface that are covered by gold or a platinum group metal, to be capable of mounting thereon one or more nitride semiconductor light-emitting elements and the like, and to have, as a whole, a predetermined planar view shape including two or more electrode pads. On the one side of the base material 11, along a boundary line between an exposed surface of the base material 11 that is not covered by the metal film 12, 13 and a side wall surface of the metal film 12, 13, at least a first part of the exposed surface of the base material 11 continuous with the boundary line that is sandwiched between two adjacent electrode pads and the side wall surfaces of the metal films 12 and 13 that oppose to each other with the first part interposed therebetween are covered by a fluororesin film 16, and a part of an upper surface of the metal film 12, 13 that composes at least the electrode pad is not covered by the fluororesin film 16.