A multilayer ceramic substrate according to the present invention includes a first insulating portion including a body of a ceramic material, a first via conductor penetrating through the body, and a first internal wiring layer and a first connection pad connected to the first via conductor; and a second insulating portion including a body of an anodized oxide material, a second via conductor penetrating through the body, and a second internal wiring layer and a second connection pad connected to the second via conductor.

A board-to-board connecting structure which adds no significant thickness to a single printed circuit board includes a first circuit board and a second circuit board. The first circuit board includes first circuit substrate, adhesive layer, and second circuit substrate. The first circuit substrate includes first base layer, first inner wiring layer with first pad, and first outer wiring layer defining a receiving space. The second circuit substrate includes insulating layer and two second outer wiring layers. A conductive via in the second circuit substrate connects the two second outer wiring layers. The second circuit board includes second base layer and also two third outer wiring layers each with a second pad. The second circuit board is laterally disposed in the receiving space and one second pad connects to the conductive via and the other to the first pad.

A wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are stacked on and contact one another. The conductive through via extends through the dam portions.

A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

A wiring body includes: a core insulating base material having a first main surface and a second main surface; a signal line and a first power supply line provided on the first main surface; a second power supply line provided on the second main surface and electrically connected to the first power supply line; a first dielectric layer laminated on the first main surface so as to embed the signal line and the first power supply line; a first ground layer provided on the first dielectric layer; a second dielectric layer laminated on the second main surface so as to embed the second power supply line; and a second ground layer provided on the second dielectric layer and sandwiching at least the signal line together with the first ground layer.

A method for producing a printed circuit board (13, 15, 16) with multilayer subareas in sections, characterized by the following steps: a) providing at least one conducting foil (1, 1′) and application of a dielectric insulating foil (3, 3′) to at least one subarea of the conducting foil; b) applying a structure of conducting paths (4, 4′) to the insulating layer (3, 3′); c) providing one further printed circuit board structure; d) joining of the further printed circuit board structure with the conducting foil (1, 1′) plus insulating layer (3, 3′) and conducting paths (4, 4′) by interposing a prepreg layer (5, 85; 18, 18′), and e) laminating the parts joined in step d) under pressing pressure and heat; and a printed circuit board produced according to this method.

Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies. An embodiment of the invention provides a method of manufacturing a printed circuit including attaching a plurality of metal layer carriers to form a first subassembly including at least one copper foil pad on a first surface, applying an encapsulation material onto the first surface of the first subassembly, curing the encapsulation material and the first subassembly; applying a lamination adhesive to a surface of the cured encapsulation material, forming at least one via in the lamination adhesive and the cured encapsulation material to expose the at least one copper foil pad, attaching a plurality of metal layer carriers to form a second subassembly, and attaching the first subassembly and the second subassembly.

There are provided an insulating film, a printed circuit board including the insulating film, and a method of manufacturing the printed circuit board. The insulating film includes a first insulating material; a second insulating material; and a metal thin film disposed between the first insulating material and the second insulating material.

A laminate substrate for receiving a semiconductor chip. Included are laminate layers stacked to form the laminate substrate, each laminate layer includes a core that includes particle-filled epoxy and a metallic layer on the core. At least one laminate layer has a radial cut through the metallic layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer. The radial cut cuts only through the metallic layer and does not cut through the core.

A wiring substrate includes a first substrate and an electronic component mounted on an upper surface of the first substrate. A first pad is formed on an uppermost wiring layer of the first substrate. A connection terminal is formed on the electronic component and is located proximate to the first pad in a plan view. The wiring substrate further includes a connection member formed on the first pad to electrically connect the first pad and the connection terminal. The connection member includes a rod-shaped core and a solder layer, which is coated around the core and joined to the first pad. The solder layer includes a bulge that spreads from the core of the connection member in a planar direction. The bulge is joined to the connection terminal of the electronic component.