Disclosed is a method of manufacturing a three-dimensional multi-layer electronic device, the method including: a unit forming process of forming a multi-layer unit including an electronic component and a circuit wiring by three-dimensional lay-out forming; and a unit lay-out process of manufacturing a three-dimensional multi-layer electronic device by laying out and integrating the multi-layer unit in a vertical direction.

A multilayer ceramic substrate includes a first insulating portion including a body of a ceramic material, a first via conductor penetrating through the body, and a first internal wiring layer and a first connection pad connected to the first via conductor, and a second insulating portion including a body of an anodized oxide material, a second via conductor penetrating through the body, and a second internal wiring layer and a second connection pad connected to the second via conductor.

A disclosed apparatus may be a circuit board that includes (1) a first unique sublaminate that includes a plurality of ground layers and a plurality of signal layers, (2) a second unique sublaminate that includes a plurality of power layers and another plurality of signal layers, and (3) a symmetry axis that bisects the circuit board between the first unique sublaminate and the second unique sublaminate, wherein the first unique sublaminate and the second unique sublaminate are distinct from one another. Various other apparatuses, systems, and methods are also disclosed.

A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

To provide an electronic circuit production method using 3D layer shaping capable of producing an electronic circuit having improved electrical properties and mechanical properties by utilizing characteristics of a fluid containing a metal particle by selectively using the fluid containing the metal particle. The electronic circuit production method using 3D layer shaping, the method including a wiring forming step of forming a wiring by applying a fluid containing a nano-sized metal nanoparticle on an insulating member and curing the applied fluid containing the metal nanoparticle; and a connection terminal forming step of forming a connection terminal electrically connected to the wiring by applying a fluid containing a micro-sized metal microparticle and curing the applied fluid containing the metal microparticle.

A component carrier includes a first stack having at least one first electrically insulating layer structure and at least one first electrically conductive layer structure, and a second stack with at least one second electrically insulating layer structure and at least one second electrically conductive layer structure. The first stack and the second stack are connected with each other so that a vertical two-dimensional electrically conductive connection is established. The first stack has a first cavity and the second stack has a second cavity, the first cavity and the second cavity being separated by at least one further electrically insulating layer structure. At least one of the first cavity and the second cavity is delimited by a wall being at least partially lined with an electrically conductive coating.

A method for manufacturing a multilayer printed wiring board includes: preparing a first wiring board that includes a circuit region formed with one or more signal lines on a main surface of a first insulating substrate; preparing a second wiring board that includes an electrically conductive layer on a main surface of a second insulating substrate; disposing a spacer at a position spaced apart from an outer edge of the circuit region by a predetermined distance along at least a part of the outer edge; disposing an adhesive layer on the circuit region so that a space is provided between the adhesive layer and the spacer; and laminating the first wiring board and the second wiring board for thermocompression bonding.

A multilayer wiring substrate includes a first wiring substrate including a plurality of stacked layers made of a thermosetting resin and having a wiring layer formed between each adjacent layers of the layers in a state in contact with the adjacent layers; a second wiring substrate made of a ceramic; and a joining layer disposed between a back surface of the first wiring substrate and a front surface of the second wiring substrate and configured to join the first wiring substrate and the second wiring substrate to each other. At least a surface of the joining layer adjacent to the second wiring substrate is made of a thermoplastic resin.

A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

A method includes forming a first redistribution line, forming a polymer layer including a first portion encircling the first redistribution line and a second portion overlapping the first redistribution line, forming a pair of differential transmission lines over and contacting the polymer layer, and molding the pair of differential transmission lines in a molding compound. The molding compound includes a first portion encircling the pair of differential transmission lines, and a second portion overlapping the pair of differential transmission lines. An electrical connector is formed over and electrically coupling to the pair of differential transmission lines.