An electrical assembly which has a multi-layer conformal coating comprising three or more layers on at least one surface of the electrical assembly, wherein the lowest layer of the multi-layer conformal coating, which is in contact with the at least one surface of the electrical assembly, is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organo-silicon compounds, (b) optionally O.sub.2, N.sub.2O, NO.sub.2, H.sub.2, NH.sub.3 and/or N.sub.2, and (c) optionally He, Ar and/or Kr; the uppermost layer of the multi-layer conformal coating is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O.sub.2, N.sub.2O, NO.sub.2, H.sub.2, NH.sub.3 and/or N.sub.2, and (c) optionally He, Ar and/or Kr; and the multi-layer coating comprises one or more layers which is obtainable by plasma deposition of a precursor mixture comprising (a) one or more hydrocarbon compounds of formula (A), (b) optionally NH.sub.3, N.sub.2O, N.sub.2, NO.sub.2, CH.sub.4, C.sub.2H.sub.6, C.sub.3H.sub.6 and/or C.sub.3H.sub.8, and (c) optionally He, Ar and/or Kr, Z.sub.1 represents C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl; Z.sub.2 represents hydrogen, C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl; Z.sub.3 represents hydrogen, C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl; Z.sub.4 represents hydrogen, C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl; Z.sub.5 represents hydrogen, C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl; and Z.sub.6 represents hydrogen, C.sub.1-C.sub.3 alkyl or C.sub.2-C.sub.3 alkenyl.

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A surface finish for a printed circuit board (PCB) and semiconductor wafer includes a nickel disposed over an aluminum or copper conductive metal surface. A barrier layer including all or fractions of a nitrogen-containing molecule is deposited on the surface of the nickel layer to make a barrier layer/electroless nickel (BLEN) surface finish. The barrier layer allows solder to be reflowed over the surface finish. Optionally, gold (e.g., immersion gold) may be coated over the barrier layer to create a nickel/barrier layer/gold (NBG) surface treatment. Presence of the barrier layer causes the surface treatment to be smoother than a conventional electroless nickel/immersion gold (ENIG) surface finish. Presence of the barrier layer causes a subsequently applied solder joint to be stronger and less subject to brittle failure than conventional ENIG.

An object of the present invention is to provide a method for producing an electroconductive laminate, which is capable of forming a metal layer having low resistance at a position corresponding to a patterned plated layer, a laminate, and an electroconductive laminate. The method for producing an electroconductive laminate of the present invention includes: a step of forming a plated layer forming layer on a base material using a predetermined plated layer forming composition; a step of subjecting the plated layer forming layer to a patternwise exposure treatment and a development treatment to form a patterned plated layer containing a portion having a line width of less than 3 m; a step of applying a plating catalyst or a precursor thereof to the patterned plated layer using an alkaline plating catalyst-applying liquid containing the plating catalyst or the precursor thereof; and a step of subjecting the patterned plated layer to which the plating catalyst or the precursor thereof has been applied to a plating treatment using a plating liquid containing aminocarboxylic acids to form a metal layer on the patterned plated layer.

A method for manufacturing traces of a printed circuit board (PCB) comprises an application of the periodic pulse reverse (PPR) pattern plating process. In the first stage, walls and bottoms in drilled holes of the PCB are modified with reduced graphene oxide (rGO) so that the vias can be formed by filling with copper and a very thin copper layer can be formed on the substrate through the electroplating process. In the second stage, a pattern of very fine traces with width/space less than 30/30 m is formed on the thin copper layer and then the traces are formed through the PPR pattern plating process. After removing unwanted copper layer, the traces with even thicknesses and square profiles are achieved and thus conform to requirements of the high density interconnection (HDI) technology.

A method for manufacturing traces of a printed circuit board (PCB) comprises an application of the periodic pulse reverse (PPR) pattern plating process. In the first stage, walls and bottoms in drilled holes of the PCB are modified with reduced graphene oxide (rGO) so that the vias can be formed by filling with copper and a very thin copper layer can be formed on the substrate through the electroplating process. In the second stage, a pattern of very fine traces with width/space less than 30/30 m is formed on the thin copper layer and then the traces are formed through the PPR pattern plating process. After removing unwanted copper layer, the traces with even thicknesses and square profiles are achieved and thus conform to requirements of the high density interconnection (HDI) technology.

A printed circuit board includes a first insulating layer; a first circuit pattern embedded in the first insulating layer; a second insulating layer disposed on the first insulating layer; a via hole penetrating at least a portion of each of the first and second insulating layers; and an adhesive layer disposed on at least a portion of a side surface of the via hole.

The invention relates to a conductive paste, comprising from 50 to 97 wt % of electrically conductive particles, 3 to 50 wt % of an organic medium and 0 to 20 wt % of a glass frit, the organic medium comprising a solvent, wherein the organic medium additionally comprises 10 to 90 wt % of a hydrocarbon-based lubricating oil and 2 to 60 wt % of a polymeric component, each based on the total amount of the organic medium, the polymeric component having a solubility of at least 100 g/kg in the lubricating oil. The invention further relates to a semiconductor device comprising a semiconductor substrate with at least one surface onto which an electrically conductive pattern is printed by using the paste.

A curable composition includes a radically polymerizable compound having a carbon-carbon unsaturated double bond in a molecule, and an insoluble phosphorus compound insoluble in the radically polymerizable compound. The insoluble phosphorus compound includes a phosphine oxide compound having two or more diphenylphosphine oxide groups in a molecule.

A method for providing a metallic coat covering a surface is disclosed, which comprises: (i) applying an electrically conductive two component binder on said surface; (ii) electrostatic spraying a metal powder on the binder applied in step (i); wherein the metal powder comprises metal particles with an average diameter less than 80 micron.

A carbene-coated metal foil is produced by applying an N-heterocyclic carbene (NHC) compound to one or more surfaces of a metal foil (e.g., an electrodeposited copper foil having a surface that is smooth and non-oxidized). The NHC compound contains a matrix-reactive pendant group that includes at least one of a vinyl-, allyl-, acrylic-, methacrylic-, styrenic-, amine-, amide- and epoxy-containing moiety capable of reacting with a base polymer (e.g., a vinyl-containing resin such as a polyphenylene oxide/triallyl-isocyanurate (PPO/TAIC) composition). The NHC compound may be synthesized by, for example, reacting a halogenated imidazolium salt (e.g., 1,3-bis(4-bromo-2,6-dimethylphenyl)-4,5-dihydro-1H-imidazol-3-ium chloride) and an organostannane having a vinyl-containing moiety (e.g., tributyl(vinyl)stannane) in the presence of a palladium catalyst. In some embodiments, an enhanced substrate for a printed circuit board (PCB) is produced by laminating the carbene-coated metal foil to a substrate that includes glass fiber impregnated with the base polymer.