A conductive slurry for plating comprises a carbon material, a dispersant, a binder, and a solvent. The carbon material, the dispersant and the binder are uniformly mixed in the solvent. The weight percentage of the carbon material is between 0.1% and 1%. The carbon material comprises a carbon nanotube, graphene, or a combination thereof. A plating method for a circuit board, which utilizes the conductive slurry, is also disclosed. The circuit board comprises at least a through hole. The plating method comprises a coating step, a first cleaning step, a first drying step, a first micro-etching step, a second cleaning step, an anti-oxidation step, a third cleaning step, a plating step, and a second drying step.

A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.

A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.

A printed circuit board, preferably for use in a fuel fill-level sensor and in a fuel fill-level measuring system, having conductor tracks formed on two sides of a ceramic substrate. The ceramic substrate has at least one metalized hole for through-contacting that connects the conductor tracks to one another. The hole of the sintered ceramic substrate is filled with a metal-containing sintering paste, which is introduced under pressure. In the fully sintered state, the paste enters into at least one integral bond with the ceramic substrate and completely fills the hole in so doing.

According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 m at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 m at the second major surface and fully fills the via between the first cavity and the second cavity.

A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

The invention relates to an aqueous alkaline cleaner solution for glass filler removal comprising: (a) at least one non-ionic surfactant selected from the group consisting of saturated branched or unbranched C5 to C12 carboxylic acid or salt thereof, wherein the concentration of the (a) at least one surfactant is from 0.9 to 1.7 g/L; (b) at least one surfactant selected from the group consisting of saturated branched or unbranched C5 to C12 alkyl having a negatively charged group selected from sulfate, sulfite, sulfonate, phosphate, phosphite and carbonate, and saturated C3-C8 alkyl amino carboxylate; (c) at least one compound having at least one hydroxyl group and at least one COC group selected from the group consisting of alkoxylated C5-C12 alkanol and glycosidic C5-C12 alkanol; and (d) alkali metal hydroxide, wherein the concentration of the (d) alkali metal hydroxide is from 65 to 200 g/L; and a method for use.

A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.

A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.