H05K2203/1438

HERMETIC METALLIZED VIA WITH IMPROVED RELIABILITY

An article includes a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and at least one via extending through the substrate from the first major surface to the second major surface over an axial length in an axial dimension. The article also includes a metal connector disposed within the via that hermetically seals the via. The article has a helium hermeticity of less than or equal to 1.010.sup.8 atm-cc/s after 1000 thermal shock cycles, each of the thermal shock cycle comprises cooling the article to a temperature of 40 C. and heating the article to a temperature of 125 C., and the article has a helium hermeticity of less than or equal to 1.010.sup.8 atm-cc/s after 100 hours of HAST at a temperature of 130 C. and a relative humidity of 85%.

VERTICAL EMBEDDED COMPONENT IN A PRINTED CIRCUIT BOARD BLIND HOLE

A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.

Fuses with integrated metals
10276337 · 2019-04-30 · ·

Fuse assemblies are disclosed. In one implementation, a fuse assembly may be disposed that includes a first portion of the second portion. The first portion may be formed of a first metal. The second portion may be formed of a second metal different from the first metal. The second metal may be copper, and the copper may be tin plated or silver plated.

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.

Hermetic metallized via with improved reliability

According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 m at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 m at the second major surface and fully fills the via between the first cavity and the second cavity.

Method for forming vias on printed circuit boards
09999137 · 2018-06-12 · ·

A method for filling a via on a printed circuit board formulates a paste as a dispersion of copper particulate that includes nanocopper particles in a solvent and a binder and depositing the paste into a via cavity formed in the printed circuit board. Heating the paste-filled cavity removes most of the solvent. The method sinters the deposited paste in the via cavity, planarizes the sintered via, and overplates the filled via with copper.

CIRCUIT BOARD DEVICE

A circuit board device of the embodiment includes: a mount board having an electronic component and a printed circuit board having at least one surface where the electronic component is mounted; a heat path arranged to a position facing the mount surface of the mount board, a sheet arranged on the mount surface, and a resin portion arranged between the sheet and the heat path. A cavity surrounded by the sheet and the mount surface is formed in a step portion between the electronic component and the printed circuit board.

MULTILAYER PRINTED CIRCUIT BOARD VIA HOLE REGISTRATION AND ACCURACY
20180110133 · 2018-04-19 ·

A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

FUSES WITH INTEGRATED METALS
20180108506 · 2018-04-19 · ·

Fuse assemblies are disclosed. In one implementation, a fuse assembly may be disposed that includes a first portion of the second portion. The first portion may be formed of a first metal. The second portion may be formed of a second metal different from the first metal. The second metal may be copper, and the copper may be tin plated or silver plated.