A circuit-forming method includes a first forming step of forming a resin layer including a recessed portion by a first discharge device configured to discharge a curable resin, and a second forming step of forming an electrode inside the recessed portion by a second discharge device, which is configured to discharge a conductive paste, by referring to a first mark formed by the first discharge device. A circuit-forming apparatus includes a first discharge device configured to form a resin layer including a recessed portion by discharging a curable resin, and a second discharge device configured to form an electrode inside the recessed portion by discharging a conductive paste by referring to a first mark formed by the first discharge device.

A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.

A connection method for a chip and a circuit board includes: placing the circuit board on the chip, the circuit board having a first surface in contact with the chip having a plurality of contacts, and the circuit board having a plurality of through holes aligned with the plurality of contacts respectively; placing a mask on a second surface of the circuit board, the mask having a plurality of openings aligned with the plurality of through holes respectively; covering a surface of the mask with a conductive adhesive to fill the plurality of through holes with the conductive adhesive; and keeping portions of the conductive adhesive that are respectively in the plurality of through holes to be spaced apart from each other. The portions of the conductive adhesive that fill the plurality of through holes remain to provide an electrical connection between the circuit board and the chip.

A substrate structure includes a substrate and a vertical conductive connector. The substrate includes a material with a heat resistance temperature of 300 C. or greater. The vertical conductive connector penetrates through the substrate. The vertical conductive connector has a bonding structure extending toward the substrate. A manufacturing method of the substrate structure is also provided.

A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure; a through cavity extending vertically through the stack delimited by sidewalls; and an electrically insulating coating material covering part of both opposing main surfaces of the stack and at least part of the sidewalls of the through cavity of the stack. Along at least one main planar direction of the cavity a change of the cavity width is provided at an intermediate portion of at least one sidewall with respect to the, preferably straight, remaining extension of the respective sidewall. There is also described a method of manufacturing a component carrier.

The layered body includes a seed layer that serves as a base for plating and that can be formed using a simple and low-cost method capable of ensuring stable quality and preventing the occurrence of scratches on the plating seed layer due to contact with a coating apparatus during application and contact with conveyor rollers. The layered body can provide good adhesion between a support and a metal layer (metal plating layer) without roughening the surface of the support. The transfer layered bodies is produced by forming a plating seed layer containing a dispersant and an electrically conductive material on a temporary support, forming a resin layer on the plating seed layer, and then allowing functional groups in the plating seed layer and functional groups in the resin layer to react with each other.

A printed wiring board includes a first conductor layer, a resin insulating layer having an opening, a second conductor layer including a seed layer and an electrolytic plating layer formed on the seed layer, and a via conductor including the seed layer and the electrolytic plating layer and connecting the first conductor and second conductor layers. The seed layer has a first portion on the surface of the insulating layer, a second portion on an inner wall surface in the opening of the insulating layer, and a third portion on a portion of the first conductor layer exposed by the opening of the insulating layer such that the first portion is thicker than the second portion and the third portion, the second portion has a first film and a second film electrically connected to the first film, and a portion of the first film is formed on the second film.

A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.

A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.