A wiring substrate includes an insulating layer having a front surface and a back surface and at least two wiring parts that are disposed at least on the front surface of the insulating layer and that are insulated from each other. At least one of the wiring parts is electrically isolated on the insulating layer. Each of the wiring parts includes a conductive base layer disposed on the front surface of the insulating layer, a conductive layer disposed on a front surface of the conductive base layer, and a conductive covering layer arranged to cover at least a portion of a front surface of the conductive layer, at least a portion of a side surface of the conductive base layer, and at least a portion of a side surface of the conductive layer. The conductive base layer and the conductive layer overlap and coincide with each other in plan view.

The purpose of the present invention is to provide an electronic component in which a copper electrode and an inorganic substrate exhibit strong adhesion to each other. A method for producing an electronic component according to the present invention comprises: an application step wherein a paste is applied onto an inorganic substrate, which paste contains copper particles, copper oxide particles and/or nickel oxide particles, and inorganic oxide particles having a softening point: a sintering step wherein a sintered body which contains at least copper is formed by means of heating in an inert gas atmosphere at a temperature that is less than the softening point of the inorganic oxide particles but not less than the sintering temperature of the copper particles; and a softening step wherein hearing is carried out in an inert gas atmosphere at a temperature that is not less than the softening point of the inorganic oxide particles.

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

The present disclosure provides systems for applying a compression load on at least part of an application specific integrated circuit (“ASIC”) ball grid array (“BGA”) package during the rework or secondary reflow process. The compression-loading assembly may include a top plate and a compression plate. The compression plate may exert a compression load on at least part of the ASIC using one or more compression mechanisms. The compression mechanisms may each include a bolt and a spring. The bolt may releasably couple the top plate to the compression plate and allow for adjustments to the compression load. The spring may be positioned on the bolt between the top plate and the compression plate and, therefore, may exert a force in a direction away from the top plate and toward the compression plate. The compression load may retain the solder joint and may prevent the solder separation defect during the reflow process.

A planar coil element of the present invention includes an insulating base film having a first surface and a second surface opposite to the first surface, a first conductive pattern deposited on the first surface side of the insulating base film, and a first insulating layer covering the first conductive pattern on the first surface side, in which the first conductive pattern includes a core body and a widening layer deposited by plating on the outer surface of the core body, the core body includes a thin conductive layer on the insulating base film, and the ratio of the average thickness of the first conductive pattern to the average circuit pitch of the first conductive pattern is 1/2 or more and 5 or less.

A method for plating a printed circuit board, includes placing a substrate, including a through hole, in contact with a plating solution and disposing the substrate to face an electrode; and applying a pulsed current to each surface of the substrate, including applying pulsed currents of opposite polarity to both surfaces of the substrate at least once and applying pulsed forward currents to both surfaces of the substrate at least once, to plate from a middle to an end of the through hole.

A connector device that includes a circuit board; a connector attached to the circuit board; a plurality of collars for external attachment; a first molded resin that is made of a first resin material whose melting point or softening point is 230° C. or less, and covers the entire circuit board and part of the connector; and a second molded resin that is welded to the first molded resin, is made of a second resin material whose melting point or softening point is higher than that of the first resin material for the first molded resin, and covers outer circumferences of the collars.

The present disclosure provides systems for applying a compression load on at least part of an application specific integrated circuit (“ASIC”) ball grid array (“BGA”) package during the rework or secondary reflow process. The compression-loading assembly may include a top plate and a compression plate. The compression plate may exert a compression load on at least part of the ASIC using one or more compression mechanisms. The compression mechanisms may each include a bolt and a spring. The bolt may releasably couple the top plate to the compression plate and allow for adjustments to the compression load. The spring may be positioned on the bolt between the top plate and the compression plate and, therefore, may exert a force in a direction away from the top plate and toward the compression plate. The compression load may retain the solder joint and may prevent the solder separation defect during the reflow process.

Low temperature processes for converting mixtures of metal inks into alloys. The alloys can be dealloyed by etching. A method comprising: depositing at least one precursor composition on at least one substrate to form at least one deposited structure, wherein the precursor composition comprises at least two metal complexes, including at least one first metal complex comprising at least one first metal and at least one second metal complex different from the first metal complex and comprising at least one second metal different from the first metal, treating the deposited structure so that the first metal and the second metal become elemental forms of the first metal and the second metal in a treated structure. Further, one can remove at least some of the first metal to leave a nanoporous material comprising at least the second metal. Precursor compositions can be formulated to be homogeneous compositions.

Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.