A manufacturing method of a display device includes: loading, on a stage, a panel assembly including: a display panel drivable to display an image, and first and second printed circuit boards attached to the display panel, end portions of the first and second printed circuit boards overlapping each other; providing a jet of air to the overlapping end portion of the second printed circuit board to raise the overlapping end portion away from and expose the end portion of the first printed circuit board; fixing the raised end portion away from the exposed end portion of the first printed circuit board; pre-processing the exposed end portion of the first printed circuit board; and aligning a distal end of the pre-processed end portion of the first printed circuit board and a distal end of the end portion of the second printed circuit board.

According to examples, a method of making a three-dimensional conductive printed part, including forming a layer of polymeric build material; selectively applying a fusing agent on a first selected area of the formed polymeric build material; selectively applying a conductive agent on a second selected area of the formed polymeric build material; and applying a solder receiving material to a portion of the first selected area and a portion of the second selected area; in which the solder receiving material is present on a surface of the conductive three-dimensional printed part is disclosed.

In a printed circuit board (1), thermal vias (19) are formed between the lower surface (A) and an upper surface (B) of the substrate plate (10) of the printed circuit board through the steps of: applying a respective solder resist mask (21, 31) to the lower surface (A) and the upper surface (B); applying solder to the lower surface (A) and reflow soldering the solder, wherein the solder penetrates into the boreholes (20) and forms convex menisci (26) protruding beyond the edge (22) of the respective boreholes on the lower surface (A); and creating regions (35) on the upper surface (B), which are freed from solder resist material, and which are intended for contacting at least one electronic component (17) on the upper surface and each of which comprise at least one of the thermal vias. Subsequently, the upper surface (B) can be provided with electrical components (17) on these regions (35). The first solder resist mask (21) has a respective region (23) that is free of solder resist on the lower surface around the edge of every borehole (20).

Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region 308 within the conductive structure. Other embodiments are described and claimed.

A planar coil element of the present invention includes an insulating base film having a first surface and a second surface opposite to the first surface, a first conductive pattern deposited on the first surface side of the insulating base film, and a first insulating layer covering the first conductive pattern on the first surface side, in which the first conductive pattern includes a core body and a widening layer deposited by plating on the outer surface of the core body, and the ratio of the average thickness of the first conductive pattern to the average circuit pitch of the first conductive pattern is ½ or more and 5 or less.

An elongated wired circuit board including a plurality of wires arranged in parallel, wherein the plurality of wires each includes a first linear portion extending in a first linear direction, a second linear portion extending in a second linear direction, and a connection portion, the connection portion includes a first side, a second side, a third side, and a fourth side, length y1 and length S satisfy 0<y1<S, length y1 extending from the first corner portion reaching the first widthwise other end edge of the first linear portion, and length S extending from the first widthwise other end edge of the first linear portion of one wire, and the predetermined angle θ satisfies 0<θ<1 deg.

Provided is a method of forming a coil pattern on at least one surface on a substrate, the method comprising forming a seed layer on at least one surface of a substrate, and forming at least two or more plating layers to cover the seed layer, wherein the two or more plating layers are formed through anisotropic plating.

A method for modifying an elongate structure including providing a fluid deposited onto the substrate, the fluid containing a dispersion of electrically polarizable nanoparticles and applying an AC voltage across a portion of the elongate structure so as to cause an alternating electric current to pass through the narrow section such that a break in the elongate structure is formed at the narrow section, the break being defined between a first broken end and a second broken end of the elongate structure, and then cause, when the break is formed, an alternating electric field to be applied to the fluid such that a plurality of the nanoparticles contained in the fluid are assembled to form a continuation of the elongate structure extending from the first broken end towards the second broken end so as to join the first and second broken ends.

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.