Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

A method for manufacturing a component carrier includes i) providing a metal layer, in particular a copper layer; ii) forming a film on the metal layer; iii) patterning the film in order to expose a part of the metal layer; iv) carrying out a first etch, thereby thinning the film and removing a further part of the exposed metal layer; and thereafter v) carrying out a second etch, thereby forming at least one metal trace that is spatially separated from the metal layer. A component carrier made by the method is further described.

The present disclosure relates to methods and apparatus for forming thin-form-factor reconstituted substrates and semiconductor device packages for radio frequency applications. The substrate and package structures described herein may be utilized in high-density 2D and 3D integrated devices for 4G, 5G, 6G, and other wireless network systems. In one embodiment, a silicon substrate is structured by laser ablation to include cavities for placement of semiconductor dies and vias for deposition of conductive interconnections. Additionally, one or more cavities are structured to be filled or occupied with a flowable dielectric material. Integration of one or more radio frequency components adjacent the dielectric-filled cavities enables improved performance of the radio frequency elements with reduced signal loss caused by the silicon substrate.

An elongated wired circuit board including a plurality of wires arranged in parallel, wherein the plurality of wires each includes a first linear portion extending in a first linear direction, a second linear portion extending in a second linear direction, and a connection portion, the connection portion includes a first side, a second side, a third side, and a fourth side, length y1 and length S satisfy 0<y1<S, length y1 extending from the first corner portion reaching the first widthwise other end edge of the first linear portion, and length S extending from the first widthwise other end edge of the first linear portion of one wire, and the predetermined angle θ satisfies 0<θ<1 deg.

A method of etching an electrically conductive layer structure during manufacturing a component carrier is provided. The method includes carrying out a first etching of at least one exposed region of an electrically conductive layer structure by a first etching composition having a photo-hardenable compound to thereby form a recess in the electrically conductive layer structure, hardening the photo-hardenable compound by irradiation with photons selectively on an upper side wall portion of the recess to thereby cover the upper side wall portion with a photo-hardened compound, carrying out a second etching by a second etching composition selectively on a side wall portion and/or bottom portion of the recess being not covered with the photo-hardened compound, and subsequently removing the photo-hardened compound from the side wall portion. In addition, a component carrier is provided.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

A plating-pattern plate is configured to transfer, to a substrate, a transfer pattern formed by electroless plating. The plating-pattern plate includes a transfer part having a transfer surface configured to have the transfer pattern be formed by electroless plating. The transfer surface of the transfer part contains iron and nickel. The plating-pattern plate provides a fine conductive pattern with stable quality.

A plating-pattern plate is configured to transfer, to a substrate, a transfer pattern formed by plating. The plating-pattern plate includes a base body and transfer parts disposed on the base body. Each of the transfer parts has a transfer surface configured to have the transfer pattern to be formed on the transfer surface by plating. The transfer parts are disposed electrically independent of one another on the base body. The plating-pattern plate provides a fine conductive pattern with stable quality.

Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.

The invention provides an electroconductive paste comprising 50-90 wt. % of copper particle, 0.5-10 wt. % of a glass frit, 0.1-5% wt. % of adhesion promoter, which is at least one selected member from the group consisting of cuprous oxide, titanium oxide, zirconium oxide, boron resinate, zirconium resinate, amorphous boron, lithium phosphate, bismuth oxide, aluminum oxide, and zinc oxide, and 5-20 wt. % of an organic vehicle. An article comprising an aluminum nitride substrate and electroconductive paste of the invention is also provided. A method of forming an electroconductive circuit comprising is also provided.