A circuit board structure includes a first dielectric layer, at least one first circuit layer, a second dielectric layer, and an insulating protection layer. The first circuit layer is mounted on the first dielectric layer, and includes at least one first circuit. The second dielectric layer is mounted on the first circuit layer, and includes at least one thermally conductive bump and at least one electrically conductive bump. The electrically conductive bump is electrically connected to the first circuit. The insulating protection layer is mounted on the second dielectric layer. The thermally conductive bump directly contacts the glass substrate. When lasering is applied to cut the glass substrate for de-bonding, the lasering heat energy can be absorbed and dissipated by the thermally conductive bump, resolving the problem of circuit de-bonding and raising the process yield. In addition, a manufacturing method of the circuit board structure is provided.

A method for manufacturing a package substrate including an insulating layer and a wiring conductor, including: forming, on one or both sides of a core resin layer, a substrate including a peelable first metal layer that has a thickness of 1-70 μm, a first insulating resin layer, and a second metal layer; forming a non-through hole reaching a surface of the first metal layer, performing electrolytic and/or electroless copper plating on its inner wall, and connecting the second and first metal layers; arranging a second insulating resin layer and a third metal layer and heating and pressurizing the first substrate to form a substrate; forming a non-through hole reaching a surface of the second metal layer, performing electrolytic and/or electroless copper plating on its inner wall, and connecting the second and third metal layers; peeling a third substrate; and patterning the first and third metal layers to form the wiring conductor.

A method for manufacturing a package substrate for mounting a semiconductor device including: a first laminate preparing step of preparing a first laminate including a resin layer, a bonding layer that is provided on at least one surface side of the resin layer and includes peeling means, and a first metal layer provided on the bonding layer; a first wiring forming step of forming a first wiring conductor in the first laminate by etching the first metal layer; a second laminate forming step of forming a second laminate by laminating an insulating resin layer and a second metal layer in this order on a surface of the first laminate, the surface being provided with the first wiring conductor; a second wiring forming step of forming a second wiring conductor on the insulating resin layer by forming a non-through hole in the insulating resin layer.

A printed circuit board includes a first insulating layer, a second insulating layer disposed on a lower surface of the first insulating layer, an electronic component embedded in the second insulating layer and at least partially in contact with the first insulating layer, a first wiring layer disposed on an upper surface of the first insulating layer, a second wiring layer disposed on a lower surface of the second insulating layer, and a first wiring via penetrating through the first and second insulating layers and connecting at least portions of the first and second wiring layers to each other.

A method for manufacturing a package substrate for mounting a semiconductor device including: a first laminate preparing step of preparing a first laminate including a resin layer, a bonding layer that is provided on at least one surface side of the resin layer and includes peeling means, and a first metal layer provided on the bonding layer; a first wiring forming step of forming a first wiring conductor in the first laminate by etching the first metal layer; a second laminate forming step of forming a second laminate by laminating an insulating resin layer and a second metal layer in this order on a surface of the first laminate, the surface being provided with the first wiring conductor; a second wiring forming step of forming a second wiring conductor on the insulating resin layer by forming a non-through hole in the insulating resin layer.

A semifinished product with a sacrificial structure and two component carriers releasably formed on opposing main surfaces of the sacrificial structure. The component carriers include at least one electrically insulating layer structure, and at least one electrically conductive layer structure. The at least one electrically insulating layer structure relates to a respective one of the component carriers. Located closest to the sacrificial structure are pure or unprocessed electrically insulating layers without electrically conductive material therein.

An arrangement, a method of manufacturing component carriers and a component carrier are provided. The arrangement includes a central carrier structure having a front side and a back side, a first layer stack having a first surface structure made of another material than the interior of the first layer stack and covered by a first release layer which is attached to the front side, and a second layer stack covered by a second release layer which is attached to the back side.

A semifinished product with a sacrificial structure and two component carriers releasably formed on opposing main surfaces of the sacrificial structure. The sacrificial structure includes a central structure and releasing layers on or over both opposing main surfaces of the central structure The central structure includes a dummy core being covered, in particular fully, on or over both main surfaces thereof with a respective one of two spatially separated sections of separate material, in particular separate dielectric material.

An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.

The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.