Patent classifications
H05K2203/1545
Transfer method for manufacturing conductor structures by means of nano-inks
A method for equipping a film material with at least one electrically conductive conductor structure, wherein a dispersion containing metallic nanoparticles in the form of a conductor structure is applied to a thermostable transfer material and the metallic nanoparticles are sintered to form an electrically conductive conductor structure. The electrically conductive conductor structure of sintered metallic nanoparticles is then transferred from the thermostable transfer material to the non-thermostable film material. A method for producing a laminate material using the film material using at least one electrically conductive conductor structure, and to the corresponding film material and laminate material are described.
Transfer method for manufacturing conductor structures by means of nano-inks
A method for equipping a film material with at least one electrically conductive conductor structure, wherein a dispersion containing metallic nanoparticles in the form of a conductor structure is applied to a thermostable transfer material and the metallic nanoparticles are sintered to form an electrically conductive conductor structure. The electrically conductive conductor structure of sintered metallic nanoparticles is then transferred from the thermostable transfer material to the non-thermostable film material. A method for producing a laminate material using the film material using at least one electrically conductive conductor structure, and to the corresponding film material and laminate material are described.
Electronic devices comprising a via and methods of forming such electronic devices
A composite article includes a conductive layer with nanowires on at least a portion of a flexible substrate, wherein the conductive layer has a conductive surface. A patterned layer of a low surface energy material is on a first region of the conductive surface. An overcoat layer free of conductive particulates is on a first portion of a second region of the conductive surface unoccupied by the patterned layer. A via is in a second portion of the second region of the conductive surface between an edge of the patterned layer of the low surface energy material and the overcoat layer. A conductive material is in the via to provide an electrical connection to the conductive surface.
DOUBLE-SIDED METAL-CLAD LAMINATE AND PRODUCTION METHOD THEREFOR, INSULATING FILM, AND ELECTRONIC CIRCUIT BASE BOARD
A method of producing a double-sided metal-clad laminate comprises a supplying step of supplying an insulating film interposed between two metal foils continuously to between a pair of endless belts, a heat and pressure applying step of forming a laminate of the insulating film and the metal foils by heating and applying a pressure to the insulating film and the metal foils under predetermined condition while the insulating film is interposed by the two metal foils in between the endless belts, and a cooling step of cooling the laminate, wherein the insulating film has a thickness of 10 to 500 μm, a degree of planar orientation of 30% or more, an average coefficient of linear expansion in an MD direction of −40 to 0 ppm/K and an average coefficient of linear expansion in a TD direction of 0 to 120 ppm/K.
Bi-layer prepreg for reduced dielectric thickness
An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.
CIRCUIT BOARD TAPE AND JOINING METHOD THEREOF
A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.
Method for producing circuit board and method for producing integrated circuit including the same
A method for producing a circuit board includes providing a substrate on which a toner image formed of a thermoplastic toner has been formed and forming a conductive foil layer having a thickness of 0.1 μm to 2 μm on the toner image that has been formed on the substrate and then applying heat to the toner image and the conductive foil layer to form a wire constituted by conductive foil.
FORMING ELECTRICAL INTERCONNECTIONS USING CAPILLARY MICROFLUIDICS
A method for manufacturing an electronic device includes providing a substrate with a first major surface having a microchannel, wherein the microchannel has a first end and a second end; dispensing a conductive liquid in the microchannel to cause the conductive liquid to move, primarily by capillary pressure, in a first direction toward the first end of the microchannel and in a second direction toward the second end of the microchannel; and solidifying the conductive liquid to form an electrically conductive trace electrically connecting a first electronic device at the first end of the microchannel to a second electronic device at the second end of the microchannel.
PROVIDING ONE OR MORE CARBON LAYERS TO A COPPER CONDUCTIVE MATERIAL TO REDUCE POWER LOSS IN A POWER PLANE
A structure includes a first copper layer and a first carbon layer applied directly to a surface of the first copper layer, a second copper layer and a second carbon layer applied directly to a surface of the second copper layer, and an insulating core disposed between the first and second copper layers. Each of the first carbon layer and the second carbon layer faces toward and directly contacts the insulating core. The structure provides electrical power to a component of an electronic device.
Electronic device testing system, electronic device production system including same and method of testing an electronic device
There is described an electronic device testing system for testing an electronic device having a substrate on which is printed a metamaterial structure using an ink. The electronic device testing system generally has: a terahertz radiation emitter configured to emit an incident terahertz radiation beam to be incident on the metamaterial structure of the substrate, the incident terahertz radiation beam having power at least at the terahertz resonance frequency of the metamaterial structure; a terahertz radiation receiver configured to receive an outgoing terahertz radiation beam outgoing from the metamaterial structure and to measure an amplitude of an electric field of the outgoing terahertz radiation beam at least at the terahertz resonance frequency; and a controller configured to determine a conductivity value indicative of a conductivity of the ink based on said amplitude of the electric field of the outgoing terahertz radiation beam.