An alignment mark includes a first alignment marker located on a first surface of a substrate and a second alignment marker located on a second surface of the substrate. The second alignment marker is arranged to be matched with the first alignment marker, and capable of representing a process variation between the second alignment marker and the first alignment marker.

A method for manufacturing a circuit board, includes: stacking a first peelable film on a second peelable film, and disposing fluffy carbon nanotubes between the first peelable film and the second peelable film, thereby obtaining a carbon nanotube layer; pressing the first peelable film, the carbon nanotube layer, and the second peelable film to compact the fluffy carbon nanotubes, thereby obtaining a thermal conductive layer; removing the first peelable film, and disposing a first adhesive layer, a first dielectric layer, and a first circuit layer on a side of the thermal conductive layer away from the second peelable film; removing the second peelable film, and disposing a second adhesive layer, a second dielectric layer, and a second circuit layer on a side of the thermal conductive layer away from the first adhesive layer; mounting an electronic component on the first circuit layer.

A component carrier with an electrically insulating layer having a front side and a back side, a first and a second electrically conductive layer covering the front side and the back side of the electrically insulating layer, respectively. A through hole extends through both electrically conductive layers and the electrically insulating layer. An overhang is formed along one of the electrically conductive layers and sidewalls of the electrically insulating layer structure delimiting the through hole. An annular plating layer covers the sidewalls and fills part of the overhang such that a horizontal extension of the overhang after plating is less than 20 μm and/or such that a ratio between a horizontal extension of the overhang after plating and a width of a first window through the first electrically conductive layer and/or a width of a second window through the second electrically conductive layer is smaller than 20%.

An electric component includes a printed circuit board with each of a pair of surfaces serving as a component mounting surface. The component mounting surface has a predetermined region on which electronic components are coated with a resin. A predetermined one of the electronic components in the region is not covered with the resin at a portion above a predetermined height from the component mounting surface.

An extremely thin copper foil is provided that enables formation of highly fine different wiring patterns with a line/space (L/S) of 10 μm or less/10 μm or less on two sides of the copper foil and is thus usable as an inexpensive and readily processable substitution for silicon and glass interposers. The extremely thin copper foil includes, in sequence, a first extremely thin copper layer, an etching stopper layer, and the second extremely thin copper layer. Two sides of the extremely thin copper foil each have an arithmetic average roughness Ra of 20 nm or less.

A transparent circuit board includes a conductive wiring, a transparent insulating layer, and a cover film. The transparent insulating layer and the cover film are stacked along a stacking direction. The conductive wiring penetrates the transparent insulating layer along the stacking direction, and is at least partially embedded in the transparent insulating layer. A blackened layer is formed on a surface of the conductive wiring combined with the cover film, a carbon black layer is formed on a surface of the conductive wiring without the blackened layer, thereby improving a light transmittance of the transparent circuit board. The present invention also provides a method for manufacturing the transparent circuit board.

A component carrier includes an electrically insulating layer structure having a first main surface and a second main surface with a through hole extending through the electrically insulating layer structure between the first main surface and the second main surface. An electrically conductive bridge structure connects opposing sidewalls of the electrically insulating layer structure delimiting the through hole. A vertical thickness of the electrically insulating layer structure is not more than 200 μm and a narrowest vertical thickness of the bridge structure is at least 20 μm.

A coreless component carrier includes (a) a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure; and (b) a component embedded in the stack. At least one electrically insulating layer structure includes a reinforced layer structure, which is arranged at an outer main surface of the stack. Further described is a method for manufacturing such a coreless component carrier and preferably simultaneously a further coreless component carrier of the same type.

A printed circuit board has an in-pad via. In a first step, a component is mounted on a first surface of a printed circuit board. A screen to be used in a second step has openings at positions corresponding to those of a plurality of pads on a second surface and has a recess positioned to overlap an in-pad via. Solder cream is applied from above the screen, and the screen is removed. Then, a component is mounted on the second surface.

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first buildup layer is over the first surface of the core, and a second buildup layer is under the second surface of the core. In an embodiment, the electronic package further comprises a via through the core between the first surface of the core and the second surface of the core, and a plane into the first surface of the core, where a width of the plane is greater than a width of the via.