Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.

A forming method of a semiconductor structure includes the following: providing a semiconductor substrate formed with a first mask layer having a preset pattern; forming a second mask layer having a first mask pattern on a surface of the first mask layer, wherein the first mask pattern includes a plurality of first sub-patterns arranged in sequence; forming a second mask pattern in the second mask layer through the first mask pattern in a self-alignment manner, wherein the second mask pattern includes the first sub-patterns of the first mask pattern and second sub-patterns corresponding to the first sub-patterns; etching the first mask layer based on the first sub-patterns and the second sub-patterns of the second mask pattern to convert the preset pattern into an active area pattern; and defining active areas in the semiconductor substrate based on the active area pattern.

A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

Apparatuses and methods for manufacturing semiconductor memory devices are described. An example method includes: forming first interconnects; forming first dielectric layers above the first interconnects in a peripheral region; removing portions of the first dielectric layers to form first openings through the first dielectric layers in the peripheral region to expose the first interconnects at bottoms of the first openings; depositing first conductive material in the peripheral region to form first contact portions in the first openings; forming second dielectric layers on the first dielectric layers and the first contact portions in the peripheral region; removing second portions of the second dielectric layers to form second openings through the second dielectric layers to expose the first contact portions at bottoms of the second openings; depositing second conductive material to form a plurality of second contact portions in the corresponding first openings; and forming second interconnects on the second contact portions.

A semiconductor structure includes a semiconductor substrate including a first active region and a chop region. The semiconductor structure also includes a source/drain region disposed in the first active region, an isolation structure disposed in the chop region, and a gate structure extending at least across the isolation structure in the chop region. The gate structure includes a gate electrode layer and a gate lining layer lining on the gate electrode layer. The gate lining layer includes a first portion having an upper surface that is lower than a bottom surface of the source/drain region.

An apparatus comprising a multilevel wiring structure comprising aluminum interconnections. The aluminum interconnections comprise a first portion, a second portion, and a third portion, where the second portion is between the first portion and the third portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. A memory device comprising a memory array comprising memory cells and a control logic component electrically connected to the memory array. At least one of the memory cells comprises a multilevel wiring structure comprising interconnect structures, where the interconnect structures comprise a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. Related apparatus, memory devices, and methods are also disclosed.

A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

A semiconductor device includes a transistor, a bit line and a bit-line via structure. The transistor is located in a transistor layer, and has a source contact and a drain contact. The bit line is electrically connected to one of the source contact and the drain contact. The bit-line via structure is located in the transistor layer, and electrically interconnects the bit line and a periphery device.

The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a pad oxide layer over a semiconductor substrate; forming a pad nitride layer over the pad oxide layer; forming a shallow trench penetrating through the pad nitride layer and the pad oxide layer and extending into the semiconductor substrate; forming a first liner, a second liner and a third liner over sidewalls and a bottom surface of the semiconductor substrate in the shallow trench; filling a remaining portion of the shallow trench with a trench filling layer over the third liner; and planarizing the second liner, the third liner and the trench filling layer to expose the pad nitride layer. The first liner and the remaining portions of the second liner, the third liner and the trench filling layer collectively form a shallow trench isolation (STI) structure in an array area.

An air gap forming method of forming an air gap in a gap structure having an upper surface, a lower surface, and a sidewall connecting the upper and lower surface, includes: repeatedly performing a selective deposition cycle, wherein the selective deposition cycle includes supplying a deposition inhibitor onto a substrate including the gap structure; and selectively forming a material layer on the upper surface compared to the sidewall.