A semiconductor device of an embodiment includes a first electrode, a second electrode, a first oxide semiconductor layer between the first electrode and the second electrode, the first oxide semiconductor layer containing in, Zn, and a first metal element, and the first metal element being at least one metal of Ga, Mg, or Mn, a second oxide semiconductor layer between the first oxide semiconductor layer and the second electrode, the second oxide semiconductor layer containing In, Zn, and the first metal element, a third oxide semiconductor layer between the first oxide semiconductor layer and the second oxide semiconductor layer, the third oxide semiconductor layer containing in, Zn, and a second metal element, the second metal element being at least one metal of Al, Hf, La, Sn, Ta, Ti, W, Y, or Zr, a gate electrode facing the third oxide semiconductor layer, and a gate insulating.

A method for manufacturing a semiconductor structure includes operations as follows. First mask pattern layers spaced apart on a base are formed. A first dielectric layer is deposited between the first mask pattern layers. The first dielectric layer is etched to form a first trench, the first trench exposing the base and a part of side walls of the first mask pattern layers. The base is etched to a first depth along the first trench, to expose the base under the first mask pattern layers. The base under the first mask pattern layers is etched to form gaps in the base.

An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.

A memory device includes a transistor, a memory cell, and an interconnect layer. The transistor includes a bottom source/drain portion, a channel portion, and a top source/drain portion stacked from bottom to top and a gate structure surrounding the channel portion. The memory cell includes a nanowire bottom electrode, a first dielectric layer, a second dielectric layer, and a top electrode. The first dielectric layer laterally surrounds the nanowire bottom electrode. The second dielectric layer is over the nanowire bottom electrode and the first dielectric layer. The second dielectric layer is in contact with a top surface of the nanowire bottom electrode and a sidewall of the first dielectric layer. The top electrode covers the second dielectric layer. The interconnect layer is over the transistor and the memory cell to interconnect the transistor and the memory cell.

Embodiments provide a semiconductor structure and a method for fabricating the same, and relate to the field of semiconductor technology. The method includes: providing a substrate provided with word line trenches and bit line trenches, where the word line trenches and the bit line trenches separate the substrate into active pillars arranged at intervals, and along a first direction, a dielectric layer is provided between adjacent active pillars; forming initial protective layers on side walls of the word line trenches; forming word line isolation structures in the region surrounded by the initial protective layers, the word line isolation structures having gaps therein; forming sealing members configured to seal up at least tops of the gaps; forming first filling regions; and forming word lines extending along the first direction in the first filling regions. Parasitic capacitance is prevented in the semiconductor structure, and performance of the semiconductor structure is improved.

A method of preparing an air gap includes: forming a first covering layer etching and removing part higher than a horizontal line where a top of the oxide layer is located; forming a first oxide layer on an etched plane; etching the first oxide layer; removing a part of the first oxide layer; reserving a rest part of the first oxide layer; taking a reserved first oxide layer as an oxide layer pattern; forming a second covering layer at a position of a removed part of the first oxide layer; removing the oxide layer pattern and the oxide layer.

Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a method for forming a unified semiconductor chip is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

IC devices implementing bilayer stacking with lines shared between bottom and top memory layers, and associated systems and methods, are disclosed. An example IC device includes a support structure, a front end of line (FEOL) layer and a back end of line (BEOL) layer. The BEOL layer includes a first memory cell in a first layer over the support structure, an electrically conductive line in a second layer, above the first layer, and a second memory cell in a third layer, above the second layer. The line could be one of a wordline, a bitline, or a plateline that is shared between the first and second memory cells. In particular, bilayer stacking line sharing is such that only one line is provided as a line to be shared between one or more of the memory cells of the first layer and one or more memory cells of the third layer.

A method of manufacturing a DRAM includes proving a substrate having active regions. First bit line structures are buried in the substrate. Each of first bit line structures extends along a first direction. Every two of the first bit line structures are disposed between two neighboring ones of the active regions arranged along a second direction. A plurality of pillar structures are formed arranged along the first direction by dividing each of the active regions. Second bit line structures are formed. Each of the second bit line structures is located between the pillar structures of a corresponding one of the active regions and extends through the corresponding one of the active regions along the second direction to be disposed on the first bit line structures at two sides of the corresponding one of the active regions and be electrically connected to the first bit line structures below.

A transistor (e.g., TFT) includes a source region and a drain region located within an insulating matrix layer, a U-shaped channel plate contacting sidewalls of the source region and the drain region, a U-shaped gate dielectric contacting inner sidewalls of the U-shaped semiconducting metal oxide plate, and a gate electrode contacting inner sidewalls of the U-shaped gate dielectric.