To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band gap of 2.5 eV or higher is used for a DRAM, so that a retention period of potentials in a capacitor can be extended. Further, a memory cell has n capacitors with different capacitances and the n capacitors are each connected to a corresponding one of n data lines, so that a variety of the storage capacitances can be obtained and multilevel data can be stored. The capacitors may be stacked for reducing the area of the memory cell.

A stacked memory device includes a plurality of lower word lines extending in a first direction, a bit line positioned over the plurality of the lower word lines and extending in a second direction intersecting with the first direction, and a plurality of upper word lines positioned over the bit line and extending in the first direction. The stacked memory device also includes a plurality of lower memory cells including a lower capacitor and a lower switching element between the lower word lines and the bit line. The stacked memory device further includes a plurality of upper memory cells including an upper capacitor and an upper switching element between the bit line and the upper word lines.

Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

According to one embodiment, a device includes: a circuit on a first surface of a substrate and including a first contact; an aluminum oxide layer above the substrate in a first direction perpendicular to the first surface; a cell including a capacitor provided in the aluminum oxide layer; a first conductive layer provided between the substrate and the aluminum oxide layer in the first direction and connected to the cell; a first insulating layer between the first conductive layer and the substrate in the first direction; a second insulating layer adjacent to the aluminum oxide layer in a second direction parallel to the first surface and provided above the substrate in the first direction; and a second contact in the second insulating layer and above the first contact in the first direction to connect the cell to the first contact.

A semiconductor device includes: a first bit line extending in a first direction; a first word line extending in a second direction intersecting the first direction; a first transistor located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line; a first capacitor electrically connected to the first transistor, the first capacitor being located at a first part of the first intersection; a second capacitor electrically isolated from the first transistor, the second capacitor being located at a second part of the first intersection; and a second transistor electrically connected to the second capacitor, the first capacitor and the second capacitor being located between the first transistor and the second transistor.

According to one embodiment, a semiconductor memory device includes a sense amplifier on a semiconductor substrate, a memory cell array including a memory cell above the sense amplifier, the memory cell including a capacitor and a first transistor, the capacitor including a first electrode and a second electrode, the first transistor including a first current path and a first control electrode controlling an on/off of the first current path, the first current path including a first terminal and a second terminal, the first terminal being electrically connected to the first electrode, and a first conductive line electrically connected to the second terminal and extending along an upper surface of the semiconductor substrate in a first direction, the first conductive line being electrically connected to the sense amplifier.

Provided are a memory structure and a method for manufacturing the same. The memory structure includes a capacitor and a transistor disposed thereon and electrically connected thereto. The transistor includes a first and a source/drain layers, a channel pillar, a gate, a gate dielectric layer, a doped layer, and a spacer layer. The first source/drain layer is electrically connected to the capacitor. The channel pillar is on the first source/drain layer. The gate is on a sidewall of the channel pillar. The gate dielectric layer is between the gate and the channel pillar. The doped layer is on the sidewall of the channel pillar and above the gate. The spacer layer is between the gate and the first source/drain layer and between the gate and the doped layer. The second source/drain layer is on or in the channel pillar.

An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

Embodiments provide a memory and a fabrication method thereof, and relates to the field of storage device technology to solve the technical problem of lower storage density of the memory. The fabrication method of the memory includes: providing a substrate including a central region and an edge region connected to each other, a first contact structure electrically connected to a wordline structure in the substrate being formed in the edge region; forming a second contact structure electrically connected to the first contact structure on the edge region; forming a capacitor structure electrically connected to the wordline structure on the central region; forming a third contact structure electrically connected to the second contact structure on the second contact structure; and forming a transistor structure electrically connected to the wordline structure on the capacitor structure and the third contact structure.

Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.