A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed.

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a pillar having an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, and a lower channel between the middle source/drain and the lower source/drain. The integrated assembly includes a gate pair that includes a first gate and a second gate. The first gate is positioned on a first side of the pillar at a first height, and the second gate is positioned on a second side of the pillar, that is opposite the first side, at a second height that is different from the first height. The integrated assembly includes a capacitor that is electrically coupled with the upper source/drain. Some implementations include methods of forming the various structures, integrated assemblies, and memory devices.

Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening.

A method of forming an elevationally-extending conductor laterally between a pair of structures comprises forming a pair of structures individually comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line and the conductive via respectively have opposing sides in a vertical cross-section. Elevationally-extending-insulative material is formed along the opposing sides of the conductive via and the conductive line in the vertical cross-section. The forming of the insulative material comprises forming a laterally-inner-insulator material comprising silicon, oxygen, and carbon laterally-outward of the opposing sides of the conductive via and the conductive line in the vertical cross-section. A laterally-intervening-insulator material comprising silicon and oxygen is formed laterally-outward of opposing sides of the laterally-inner-insulator material in the vertical cross-section. The laterally-intervening-insulator material comprises less carbon, if any, than the laterally-inner-insulator material. A laterally-outer-insulator material comprising silicon, oxygen, and carbon is formed laterally-outward of opposing sides of the laterally-intervening-insulator material in the vertical cross-section. The laterally-outer-insulator material comprises more carbon than the laterally-inner-insulator material. Elevationally-extending-conductor material is formed laterally between and along the insulative material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a first metal silicon nitride layer on the silicon layer; performing an oxygen treatment process to form an oxide layer on the first metal silicon nitride layer; forming a second metal silicon nitride layer on the oxide layer; forming a conductive layer on the second metal silicon nitride layer; and patterning the conductive layer, the second metal silicon nitride layer, the oxide layer, the first metal silicon nitride layer, and the silicon layer to form a gate structure.

An integrated circuit device includes: a conductive line structure including a conductive line and an insulating capping pattern; and an insulating spacer including an inner spacer and a first insulating spacer, the inner spacer and the first insulating spacer on a sidewall of the conductive line structure. The first insulating spacer includes: a slit portion; a lower insulating portion spaced apart from the inner spacer such that a separation distance between a portion of the lower insulating portion and the inner spacer decreases with increasing vertical distance from the substrate; and an upper insulating portion contacting the inner spacer. A method of forming the insulating spacer includes: forming a polymer layer on the inner spacer; forming a first insulating spacer layer which contacts each of the inner spacer and the polymer layer; and forming a first insulating spacer by partially removing the first insulating spacer layer.

A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.