A memory cell comprising a substrate, a bit line vertically oriented from the substrate along a first direction, a nanosheet transistor including at least one nanosheet horizontally oriented from the bit line along a second direction perpendicular to the first direction, and a capacitor horizontally oriented from the nanosheet transistor along the second direction.

A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

An edge memory array mat with access lines that are split, and a bank of sense amplifiers formed under the edge memory array may in a region that separates the access line segment halves. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes access line connectors configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

A method used in forming integrated circuitry comprises forming conductive line structures having conductive vias laterally between and spaced longitudinally along immediately-adjacent of the conductive line structures. First insulating material is formed laterally between immediately-adjacent of the conductive vias, Second insulating material is formed directly above the first insulating material and directly above the conductive vias. The second insulating material comprises silicon, carbon, nitrogen, and hydrogen. A third material is formed directly above the second insulating material. The third material and the second insulating material comprise different compositions relative one another. The third material is removed from being directly above the second insulating material and the thickness of the second insulating material is reduced thereafter. A fourth insulating material is formed directly above the second insulating material of reduced thickness. A plurality of electronic components is formed above the fourth insulating material and that individually are directly electrically coupled to individual of the conductive vias through the fourth and second insulating materials. Other embodiments, including structure, are disclosed.

Some embodiments relate to a memory device including first and second conductive lines extending generally in parallel with one another within over a row of memory cells. A centerline extends generally in parallel with the first and second conductive lines and is spaced between the first and second conductive lines. A first plurality of conductive line segments is over the first conductive line. Conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line. A second plurality of conductive line segments are disposed over the second conductive line, and are coupled to different locations on the second conductive line.

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed.

A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

A semiconductor memory device including an access transistor configured as a vertical transistor comprises a channel portion and a pair of source/drain regions; a storage capacitor connected to one of the pair of source/drain regions; a bit line connected to the other of the pair of source/drain regions, a first semiconductor layer provided in the source/drain region to which the bit line is connected. Preferably, the first semiconductor layer comprises SiGe.

The invention discloses a NOR-type memory device and a method of fabricating such NOR-type memory device. The NOR-type memory device according to a preferred embodiment of the invention includes a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of multi-layer stripes, a plurality of memory cells, a plurality of first sub-bit lines, a plurality of second sub-bit line, a plurality of word lines, an insulating layer, a plurality of grounded via contacts, and a grounding layer. The first isolation stripes and the second isolation stripes extend in a longitudinal direction defined by the semiconductor substrate. Each memory cell corresponds to one of the columns and one of the rows defined by the semiconductor substrate. The memory cells on one side of each first isolation stripe and the memory cells on the other side of said one first isolation stripe are staggeredly arranged. Each word line corresponds to one of the columns and connects the gate conductors of the memory cells along the corresponding column. The insulating layer is formed on the multi-layer stripes, the first isolation stripes and the second isolation stripes. Each of the grounded via contacts corresponds to one of the second sub-bit lines, and is formed through the insulating layer to connect the corresponding second sub-bit line. The grounding layer is formed on the insulating layer to connect all of the grounded via contacts.