Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

[PROBLEM] An object of the present invention is to provide a nonvolatile memory device having an excellent information retention characteristic, exhibiting high performance, and achieving practical mass-production, and a manufacturing method therefor.

[SOLUTION] A nonvolatile memory device 1 has a laminated structure part including a plurality of Al.sub.2O.sub.3 layers 4 and a plurality of SiO.sub.2 layers 6 formed as two types of insulating layers formed with different compositions and disposed alternately, and an O-M.sub.1-O layer 5 of a 0.5 molecular layer to a 2.0 molecular layer, formed by a chemical bond between a metal element M.sub.1 and oxygen, and disposed on each joining interface between the insulating layers, the metal element M.sub.1 being an element other than elements constituting the insulating layers, and the nonvolatile memory device stores information by modulating an interface dipole induced in the vicinity of the O-M.sub.1-O layer 5 by external electrical stimulation.

[PROBLEM] An object of the present invention is to provide a nonvolatile memory device having an excellent information retention characteristic, exhibiting high performance, and achieving practical mass-production, and a manufacturing method therefor.

[SOLUTION] A nonvolatile memory device 1 has a laminated structure part including a plurality of Al.sub.2O.sub.3 layers 4 and a plurality of SiO.sub.2 layers 6 formed as two types of insulating layers formed with different compositions and disposed alternately, and an O-M.sub.1-O layer 5 of a 0.5 molecular layer to a 2.0 molecular layer, formed by a chemical bond between a metal element M.sub.1 and oxygen, and disposed on each joining interface between the insulating layers, the metal element M.sub.1 being an element other than elements constituting the insulating layers, and the nonvolatile memory device stores information by modulating an interface dipole induced in the vicinity of the O-M.sub.1-O layer 5 by external electrical stimulation.

The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

Source terminals of memory devices and related apparatuses, computing systems, and methods are disclosed. An apparatus includes a first polysilicon material, a second polysilicon material offset from the first polysilicon material, an intervening polysilicon material between the first polysilicon material and the second polysilicon material, and pillars defining memory cells. The pillars extend through the second polysilicon material and a proximal portion of the intervening polysilicon material into the first polysilicon material. The one or more insulative materials are at a distal edge of the intervening polysilicon material. The intervening polysilicon material is thicker at the distal edge than at the pillars. A method includes removing, using an isotropic etch process, portions of the first polysilicon material and the second polysilicon material in a trench and forming the intervening polysilicon material between the first polysilicon material and the second polysilicon material.

Source terminals of memory devices and related apparatuses, computing systems, and methods are disclosed. An apparatus includes a first polysilicon material, a second polysilicon material offset from the first polysilicon material, an intervening polysilicon material between the first polysilicon material and the second polysilicon material, and pillars defining memory cells. The pillars extend through the second polysilicon material and a proximal portion of the intervening polysilicon material into the first polysilicon material. The one or more insulative materials are at a distal edge of the intervening polysilicon material. The intervening polysilicon material is thicker at the distal edge than at the pillars. A method includes removing, using an isotropic etch process, portions of the first polysilicon material and the second polysilicon material in a trench and forming the intervening polysilicon material between the first polysilicon material and the second polysilicon material.