A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a single crystalline semiconductor layer, a single crystal epitaxial source semiconductor layer located between the single crystalline semiconductor layer and the alternating stack and epitaxially aligned to the single crystalline semiconductor layer, and a memory stack structure vertically extending through the alternating stack and containing a memory film and an epitaxial vertical semiconductor channel including a single crystal semiconductor material that is epitaxially aligned to the epitaxial source semiconductor layer at an interface.

The present disclosure relates to a flash memory structure. The flash memory structure includes a first doped region and a second doped region disposed within a substrate. A select gate is disposed over the substrate between the first doped region and the second doped region. A floating gate is disposed over the substrate between the select gate and the first doped region, and a control gate is over the floating gate. The floating gate extends along multiple surfaces of the substrate.

According to an embodiment, a semiconductor memory device includes first and second groups each including a plurality of memory cells, and a control circuit. The control circuit is configured to successively apply a first voltage and a second voltage which is higher than the first voltage to a memory cell in the first or second group, and to apply a third voltage to the memory cell after applying the second voltage. When the memory cell is included in the first group, the control circuit applies the third voltage to the memory cell a time earlier with respect to a time when the second voltage is applied than when the memory cell is included in the second group. Each of the first and second groups corresponds to a data erase unit or a unit larger than the data erase unit.

According to an embodiment, a semiconductor memory device includes first and second groups each including a plurality of memory cells, and a control circuit. The control circuit is configured to successively apply a first voltage and a second voltage which is higher than the first voltage to a memory cell in the first or second group, and to apply a third voltage to the memory cell after applying the second voltage. When the memory cell is included in the first group, the control circuit applies the third voltage to the memory cell a time earlier with respect to a time when the second voltage is applied than when the memory cell is included in the second group. Each of the first and second groups corresponds to a data erase unit or a unit larger than the data erase unit.

A semiconductor device includes a substrate, a fin structure, an insulating layer, a select gate, a memory gate, and a charge trapping layer. The fin structure includes a first portion and a second extend from the substrate. Each of the first portion and the second portion includes a first sidewall and a second sidewall, and the second sidewalls are between the first sidewalls. The insulating layer is disposed between the second sidewalls of the first and second portions. The select gate and the memory gate extend across the fin structure and the insulating layer. The charge trapping layer is disposed between the memory gate and the select gate, between the memory gate and the insulating layer, and between the memory gate and the fin structure, and the second sidewalls of the first and second portions are free from in contact with the charge trapping layer.

According to one embodiment, a semiconductor storage device includes: a substrate; a plurality of first gate electrodes arranged in a first direction intersecting with a substrate surface; a first semiconductor film extending in the first direction and facing the plurality of first gate electrodes; a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film; a second gate electrode disposed farther away from the substrate than the plurality of first gate electrodes; a second semiconductor film that extends in the first direction, faces the second gate electrode, and has, in the first direction, one end connected to the first semiconductor film; and a second gate insulating film provided between the second gate electrode and the second semiconductor film. The second gate electrode includes: a first portion; and a second portion provided between the first portion and the second semiconductor film, and facing the second semiconductor film. At least a portion of the second portion is provided closer to a side of the substrate than a surface of the first portion on the side of the substrate side in the first direction.

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

In some embodiments, the present disclosure relates to a flash memory structure. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source region and the drain region, and a floating gate is disposed over the substrate between the select gate and the source region. A control gate is disposed over the floating gate. The floating gate has sidewalls that define protrusions extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.

In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.