A composite selector electrode includes a switching layer coupled in electrical parallel with a conducting layer. The switching layer is electrically insulating when the temperature of the switching layer is below a threshold temperature. The switching layer exhibits insulator-metal transition at the threshold temperature. The switching layer is electrically conducting when the temperature of the switching layer is above the threshold temperature.

Provided in one example is a nonvolatile memory crossbar array. The array includes a number of junctions formed by a number of row lines intersecting a number of column lines; and a resistive memory element in series with a selector at each of the junctions coupling between one of the row lines and one of the column lines. The selector may be a volatile switch including: a bottom electrode; an oxide layer disposed over the bottom electrode, the oxide layer including Cu.sub.2O; and a top electrode disposed over the oxide layer.

A technique disclosed in the present specification relates to reducing failures at repairing a bright pixel defect to be a dark pixel. An array substrate for a display apparatus, in this technique includes an insulating substrate that is transparent, an insulating film at least partly disposed on an upper surface of the insulating substrate and containing silicon oxide or metal oxide as a main component, a first conductive film, a second conductive film spaced apart from the first conductive film, and an insulator portion that is in direct contact with and extends between the first conductive film and the second conductive film. The insulator portion is formed by converting an oxide semiconductor film into an insulator. The insulator portion includes an upper surface or lower surface in direct contact with the insulating film.

A circuit component that exhibits a region of negative differential resistance includes: a first layer of material; and a second layer of material in contact with the first layer of material, the contact forming a first self-heating interface. The first self-heating interface is structured such that an electrical current flowing from the first layer of material to the second layer of material encounters an electrical impedance occurring at the first interface that is greater than any electrical impedance occurring in the first and second layers of material, wherein heating occurring at the first interface is dominated by Joule heating caused by the electrical impedance occurring at the first interface, and wherein the electrical impedance occurring at the first interface decreases with increasing temperature to induce a region of negative differential resistance.

Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.

A semiconductor memory device according to an embodiment comprises: a semiconductor substrate which extends in first and second directions; first wiring lines which are arranged in a third direction, and which extend in the first direction; second wiring lines which are arranged in the first direction and extend in the third direction; and memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells including a first film and a second film whose permittivity is different from that of the first film which are stacked in the second direction between one of the first wiring lines and one of the second wiring lines, and the second films of two of the memory cells adjacent in the third direction being separated between the two memory cells.

Disclosed is a solid state memory having a non-linear current-voltage (I-V) response. By way of example, the solid state memory can be used as a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the nonvolatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

A first electrode and an insulation material layer are sequentially formed over a substrate. A doping mask pattern is formed over the insulation material layer. The doping mask pattern exposes a portion of the insulation material layer. Dopants are injected into the exposed portion of the insulation material layer. The doping mask pattern is removed. A second electrode layer is formed over the insulation material layer. One or more pillar-shaped structures, each of which includes a second electrode, an insulation layer and a first electrode formed by respectively patterning the second electrode layer, the insulation material layer, and the first electrode layer. Each of the one or more pillar-shaped structures includes, in the insulation layer, a part of the exposed portion of the insulation material layer that is doped with the dopants. A threshold switching operation is performed in a region doped with the dopants of the insulation layer.

At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.

The invention relates to a non-volatile resistive random access memory (ReRAM), a non-volatile ReRAM composition and to a method for manufacturing a non-volatile non-volatile ReRAM. The ReRAM includes a first electrode, a second electrode and a resistive switching/active layer which is located between the first and second electrodes. The switching layer contains chitosan and aluminium doped/incorporated zinc oxide. The switching/active layer may be configured to perform a switching operation according to an applied voltage. The switching/active layer may be in the form of a film. The switching/active layer may be coated/applied onto the first electrode and the second electrode may be placed/applied/provided over the switching/active layer such that the switching/active layer is located/wedged in-between the two electrodes.