In an embodiment a method for convolutional computation (CNVL) of input values with weight factors includes converting the input values to voltage signals and successively applying the voltage signals on selected bit lines in an array of non-volatile memory points over respective time slots, each memory point comprising a phase-change resistive memory cell coupled to a bit line and having a resistive state corresponding to a weight factor, and a bipolar selection transistor coupled in series with the phase-change resistive memory cell and having a base terminal coupled with a word line, wherein the respective voltage signals bias the respective phase-change memory cells, integrating over the successive time slots read currents resulting from the voltage signals biasing the respective phase-change resistive memory cells and flowing through selected word lines and converting the integrated read currents to output values.

Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a bipolar junction transistor including a base, a first terminal having a first raised semiconductor layer over the base, and a second terminal having a second raised semiconductor layer over the base. The first raised semiconductor layer is spaced in a lateral direction from the second raised semiconductor layer. The structure further comprises a resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. The first electrode of the resistive memory element is coupled to the first terminal of the bipolar junction transistor.

A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.

An electronic device includes a semiconductor substrate, an insulating layer on and in contact with the semiconductor substrate, and a memory circuit including a plurality of memory cells. Each memory cell includes a bipolar selection transistor disposed in and on the semiconductor substrate, each bipolar selection transistor including a base region, an emitter region, and a collector region. Each bipolar selection transistor includes an insulation structure made of a first dielectric material, the insulation structure including an upper part extending vertically through the insulating layer, and a lower part extending vertically through the semiconductor substrate between the base region and the emitter region. The side faces of the upper part of the insulation structure are covered by spacers made of a second dielectric material.

Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a substrate having a top surface, a trench isolation region in the substrate, and a base layer on the top surface of the substrate. The base layer extending across the trench isolation region. A first bipolar junction transistor includes a first collector in the substrate and a first emitter on a first portion of the first base layer. The first portion of the first base layer is positioned between the first collector and the first emitter. A second bipolar junction transistor includes a second collector in the substrate and a second emitter on a second portion of the first base layer. The second portion of the first base layer is positioned between the second collector and the second emitter.

Provided are a semiconductor device and a method of fabricating the same.

The semiconductor device includes a semiconductor substrate, a first and a second diffusion region formed under a surface of the semiconductor substrate, a gate and a sidewall spacer stacked on the semiconductor substrate, wherein the first diffusion region is at least one active region not being intersected by the gate and the sidewall spacer, wherein the second diffusion region includes a part of an active region intersecting the gate and the sidewall spacer, wherein there is no gate insulating layer between the gate and the semiconductor substrate.