Patent classifications
H10K71/211
DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
A display apparatus is provided which may include a substrate including a display area and a non-display area adjacent to the display area, a first thin-film transistor disposed on the substrate and including a first semiconductor layer including an oxide semiconductor material, and a second thin-film transistor disposed on the substrate and including a second semiconductor layer including a silicon semiconductor material, wherein a surface roughness of the first semiconductor layer is increased by plasma treatment. A method of manufacturing the display apparatus is also provided.
Manufacturing method of OLED display panel with cathode metal layer of lower conductivity and OLED display panel
The manufacturing method provided by this application comprises: providing a substrate on which a plurality of pixel defining layers are arranged at intervals; disposing a hole injection layer on the substrate; disposing a hole transport layer on the hole injection layer; disposing an organic light emitting layer on the hole transport layer; disposing an electron transport layer on the organic light emitting layer and the pixel defining layers; and disposing a cathode metal layer on the electron transport layer, wherein the cathode metal layer comprises a first area located above the pixel defining layers; and processing the cathode metal layer in the first area.
NANOPARTICLE, METHOD FOR PATTERNING NANOPARTICLE LAYER AND LIGHT EMITTING DEVICE
The present application can provide a nanoparticle, a method for patterning a nanoparticle layer and a light emitting device. When the nanoparticle provided by the present application is adopted for manufacturing a light emitting layer of the light emitting device, a cross-linking reaction occurs among first ligands of adjacent nanoparticles under irradiation of ultraviolet light, and the cross-linked nanoparticles may be firmly connected to a front film layer of the light emitting layer, so that when a developing solution is adopted for developing treatment, the cross-linked nanoparticles are not insoluble in the developing solution and are retained while non-cross-linked nanoparticles are dissolved in the developing solution and are separated from the front film layer to be removed, therefore completing patterning of the nanoparticle layer.
Patterned nanoparticle structures
Aspects relate to patterned nanostructures having a feature size not including film thickness of below 5 microns. The patterned nanostructures are made up of nanoparticles having an average particle size of less than 100 nm. A nanoparticle composition, which, in some cases, includes a binder, is applied to a substrate. A patterned mold used in concert with electromagnetic radiation function to manipulate the nanoparticle composition in forming the patterned nanostructure. In some embodiments, the patterned mold nanoimprints a pattern onto the nanoparticle composition and the composition is cured through UV or thermal energy, Three-dimensional patterned nanostructures may be formed. A number of patterned nanostructure layers may be prepared and joined together. In some cases, a patterned nanostructure may be formed as a layer that is releasable from the substrate upon which it is initially formed. Such releasable layers may be arranged to form a three-dimensional patterned nanostructure for suitable applications.
Display panel and method for manufacturing the same
A display panel has an irregular display area and includes a substrate, a first electrode layer, a first organic-material layer, and a second electrode layer. The first electrode layer is disposed on the substrate. The first organic-material layer is disposed on the first electrode layer, in which the first organic-material layer includes a first portion and a second portion which are connected to each other. The second electrode layer is disposed on the first electrode layer. The first organic-material layer is configured to produce electroluminescence phenomenon by a bias applied by the first and second electrode layers, and the first portion has brightness less than that of the second portion under the bias.
Display panel
An embodiment of the present disclosure provides a display panel having a non-rectangular display region. The display panel includes a substrate, a pixel definition layer, a first organic material layer, and a second organic material layer. The pixel definition layer is disposed on the substrate, and defines a first pixel area and a second pixel area on the substrate. The first organic material layer is disposed in the first pixel area and has a first light-emitting region. The second organic material layer is disposed in the second pixel area and has a second light-emitting region. The first organic material layer and the second organic material layer have the same material and the same vertical projection area on the substrate, and the vertical projection area of the first light-emitting region on the substrate is smaller than the vertical projection area of the second light-emitting region on the substrate.
OPTIMUM WARP IN ORGANIC SUBSTRATES
An organic substrate and method of making with optimal thermal warp characteristics is disclosed. The organic substrate has one or more top layers and one or more bottom layers. A chip footprint region is a surface region on each of the top and bottom layers that is defined as the projection of one or more semiconductor chips (chips) on the surface of each of the top and bottom layers. One or more top removal patterns are located on and may or may not remove material from the surface of one or more of the top layers within the chip footprint region of the respective top layer. One or more bottom removal patterns are located on and remove material from the surface of one or more of the bottom layers outside the chip footprint region of the respective bottom layer. The removal of the material from one or more of the top layers and/or bottom layers changes and optimizes a thermal warp of the organic substrate. In some embodiments, a Shape Inversion Temperature (SIT) of the substrate is made equal to or above a reflow temperature.
METHOD FOR PRODUCING BASE FOR METAL MASKS, METHOD FOR PRODUCING METAL MASK FOR VAPOR DEPOSITION, BASE FOR METAL MASKS, AND METAL MASK FOR VAPOR DEPOSITION
A rolled metal sheet includes an obverse surface and a reverse surface that is a surface located opposite to the obverse surface. At least either one of the obverse surface and the reverse surface is a processing object. A method for manufacturing a metal mask substrate includes reducing a thickness of the rolled metal sheet to 10 μm or less by etching the processing object by 3 μm or more by use of an acidic etching liquid, and roughening the processing object so that the processing object becomes a resist formation surface that has a surface roughness Rz of 0.2 μm or more, thereby obtaining a metal mask sheet.
PATTERNED NANOPARTICLE STRUCTURES
Aspects relate to patterned nanostructures having a feature size not including film thickness of below 5 microns. The patterned nanostructures are made up of nanoparticles having an average particle size of less than 100 nm. A nanoparticle composition, which, in some cases, includes a binder, is applied to a substrate. A patterned mold used in concert with electromagnetic radiation function to manipulate the nanoparticle composition in forming the patterned nanostructure. In some embodiments, the patterned mold nanoimprints a pattern onto the nanoparticle composition and the composition is cured through UV or thermal energy, Three-dimensional patterned nanostructures may be formed. A number of patterned nanostructure layers may be prepared and joined together. In some cases, a patterned nanostructure may be formed as a layer that is releasable from the substrate upon which it is initially formed. Such releasable layers may be arranged to form a three-dimensional patterned nanostructure for suitable applications.
Cross-point array of polymer junctions with individually-programmed conductances
Programmable memory devices having a cross-point array of polymer junctions with individually-programmed conductances are provided. In one aspect, a method of forming a memory device includes: forming first metal lines on an insulating substrate; forming polymeric resistance elements on the first metal lines; and forming second metal lines over the polymeric resistance elements with a single one of the polymeric resistance elements present at each intersection of the first/second metal lines forming a cross-point array. A memory device and a method of operating a memory device are also provided.