The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.

A method for fabricating a single electron transistor is provided. A substrate includes a substantially planar surface with a source electrode, a drain electrode, and a gate electrode thereon, with the source and drain electrodes spaced apart from one another by a gap. The source electrode and the drain electrode are electrified, and a single nanometer-scale conductive particle is electrospray deposited in the gap. The single nanometer-scale conductive particle has an effective size of not greater than 10 nanometers. At least one carbon nanotube is deposited on the substrate and subjected to dielectrophoresis to position the carbon nanotube within 1 nanometer of the single nanometer-scale conductive particle. The at least one carbon nanotube establishes a first connection between the source electrode and the single nanometer-scale conductive particle and a second connection between the drain electrode and the single nanometer-scale conductive particle.

A polymer solar cell includes a photoactive layer, a cathode electrode, and an anode electrode. The photoactive layer includes a polymer layer and a carbon nanotube layer. The polymer layer includes a first polymer surface and a second polymer surface opposite to the first polymer surface. A portion of the carbon nanotube layer is embedded in the polymer layer, and another portion of the carbon nanotube layer is exposed from the polymer layer. The cathode electrode is located a surface of the carbon nanotube layer away from the polymer layer. The anode electrode is located on the first polymer surface and spaced apart from the carbon nanotube layer. The entire second polymer surface is exposed.

An imaging device including a semiconductor substrate including a first surface that receives light from outside, and a second surface opposite to the first surface; a first transistor located on the second surface; and a photoelectric converter that faces the second surface and that receives light transmitted through the semiconductor substrate. The semiconductor substrate is a silicon substrate or a silicon compound substrate, and the photoelectric converter includes a first electrode electrically connected to the first transistor, a second electrode, and a photoelectric conversion layer that is located between the first electrode and the second electrode and that contains a material which absorbs light having a first wavelength longer than or equal to 1.1 μm, and the material has a quantum nanostructure.

The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.

A field effect transistor and a preparation method thereof, and a semiconductor structure are provided. An example field effect transistor includes: a substrate structure, a source, a drain, and a gate. The source and the drain are arranged on the substrate structure in a first direction, and a channel region is formed between the source and the drain. A channel layer is formed in the channel region, and N carbon nanotubes extending in the first direction are embedded in the channel layer, where N is an integer greater than or equal to 1. Two ends of each of the N carbon nanotubes are respectively connected to the source and the drain to form a conductive path. The gate is formed on the channel layer. In the channel region between the source and the drain, electron conduction is implemented by using the carbon nanotube disposed in the channel layer.

A method of p-type doping a carbon nanotube includes the following steps: providing a single carbon nanotube; providing a layered structure, wherein the layered structure is a tungsten diselenide film or a black phosphorus film; and p-type doping at least one portion of the carbon nanotube by covering the carbon nanotube with the layered structure.

There is provided a photovoltaic device that comprises a front electrode, a back electrode, and disposed between the front electrode and the back electrode, an electron transporter region comprising an electron transporter layer; a hole transporter region comprising a hole transporter layer, and a layer of perovskite semiconductor disposed between and in contact with the electron transporter layer and the hole transporter layer. The electron transporter region is nearest to the front electrode and the hole transporter region is nearest to the back electrode, and the electron transporter layer comprises any of a chalcogenide material and an organic material and has a thickness of at least 2 nm.

The invention relates to a method for manufacture of an electrical contact on a structure (10) made of an anisotropic material NA which exhibits an anisotropic electrical conductivity, where the structure (10) exhibits an axial electrical conductivity along a first axis XX′ of the structure (10) and an orthogonal conductivity along a direction YY′ orthogonal to the first axis XX′ of the structure (10), where the orthogonal conductivity is less than the axial conductivity, where the method comprises: a step for the formation of a conductive electrode (20), with an initial thickness Ei, comprising a species M, on a first surface (30) of the structure (10), where the first surface (30) is orthogonal to the orthogonal direction YY′; the method being characterized in that the step for the formation of the conductive electrode (20) is followed by a step for implantation of species X through the conductive electrode (20), into the structure (10).

The present disclosure relates to a flexible display device, and according to an aspect of the present disclosure, a flexible display device includes a display panel including a folding area and a non-folding area; a back plate which is disposed below the display panel and supports the display panel; and a bottom plate which is disposed below the back plate and includes a plurality of grooves so as to correspond to the folding area, and a plurality of nano helix structures disposed so as to correspond to the plurality of grooves. Therefore, the flexible display device forms a groove pattern in the bottom plate, and includes a nano helix structure in each of the plurality of grooves, to effectively relieve the folding stress and reduce the visibility of the pattern, finally an appearance quality may be improved.