In various embodiments, superconducting wires incorporate diffusion barriers composed of Nb alloys or Nb—Ta alloys that resist internal diffusion and provide superior mechanical strength to the wires.

A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

A monofilament (100) for producing an Nb.sub.3Sn-containing superconductor wire (33) includes a powder core (1) with an Sn-containing powder, a reaction tube (3) composed of an Nb alloy that includes Nb and at least one further alloy component X. The powder core is disposed within the reaction tube. The monofilament also includes at least one source (4) for at least one partner component Pk. A respective source includes one or more source structures at a unitary radial position in the monofilament. The alloy component X and the partner component Pk form precipitates XPk on reaction annealing of the monofilament in which Sn from the powder core and Nb from the reaction tube react to produce Nb.sub.3Sn. The powder core is disposed in a moderation tube, which in turn is disposed within the reaction tube. This provides a monofilament for a powder-in-tube based Nb.sub.3Sn-containing superconductor wire with improved current carrying capacity.

In various embodiments, superconducting wires incorporate diffusion barriers composed of Nb alloys or Nb—Ta alloys that resist internal diffusion and provide superior mechanical strength to the wires.

Disclosed are a quantum chip test structure and a fabrication method therefor, and a test method and a fabrication method for a quantum chip. The quantum chip test structure includes: a superconducting Josephson junction and a connection structure of the superconducting Josephson junction that are located on a substrate; a first isolation layer located on the connection structure, where a connection window penetrating through the first isolation layer is formed in the first isolation layer; a second isolation layer located on the first isolation layer, where a deposition window is formed in the second isolation layer; and an electrical connection portion located in the connection window and an electrical connection layer located in the deposition window, and the electrical connection layer is configured to implement electrical contact with a test device.

Techniques regarding qubit structures comprising ion implanted Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a strip of superconducting material coupling a first superconducting electrode and a second superconducting electrode. The strip of superconducting material can have a first region comprising an ion implant and a second region that is free from the ion implant.

Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm.sup.2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

A system and method for treating a cavity comprises preparing a superconducting radio frequency (SRF) cavity for removal of a dielectric layer from on an inner surface of the SRF cavity, subjecting the SRF cavity to a heat treatment in order to remove the dielectric layer from the inner surface of the SRF cavity, and preventing the development of a new dielectric layer on the inner surface of the SRF cavity by preventing an interaction between the inner surface of the SRF cavity and atmospheric gasses.

In various embodiments, superconducting wires feature assemblies of clad composite filaments and/or stabilized composite filaments embedded within a wire matrix. The wires may include one or more stabilizing elements for improved mechanical properties.