A method for fabricating an active cooling structure, comprising forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer may comprise a plurality of non-superconducting traces running in a first direction. The superconductor layer may comprise a plurality of superconducting traces running in a second direction.

A method is provided of forming a superconductor device interconnect structure. The method comprises forming a first dielectric layer overlying a substrate and forming a superconducting interconnect element in the first dielectric layer. The superconducting interconnect element includes a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The superconductor device interconnect structure is moved into a dielectric deposition chamber. The method further comprises performing a cleaning process on a top surface of the first interconnect layer in the dielectric deposition chamber to remove oxidization from a top surface of the first interconnect layer, and depositing a second dielectric layer over the first interconnect layer in the dielectric deposition chamber.

A superconductor device according to some embodiments comprises a superconductor stack, which includes a superconductor layer and a silicon cap layer over the superconductor layer, the cap layer including amorphous silicon. The superconductor device further comprises a metal contact over a portion of the silicon cap layer and electrically-coupled to the superconductor layer. The metal contact comprises a core including a first metal, and an outer layer around the core that includes a second metal. The portion of the silicon cap layer is converted from silicon to a conductive compound including the second metal to provide low-resistance electrical coupling between the superconductor layer and the metal contact. The superconductor device further comprises a waveguide, and the first portion of the cap layer under the metal contact is at a sufficient lateral distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

The present invention relates to an integrated reflective backshort fabricated with a phononic-isolated kinetic inductance detector or transition edge sensor. The integrated backshort includes: a silicon wafer; a reflective metal layer bonded to the silicon wafer; a silicon first layer disposed on the reflective metal layer; a structural second layer disposed on the first layer; a first superconductor layer disposed on the second layer as a kinetic inductance detector; and a second superconductor layer disposed on the second layer as leads, a microstrip, a capacitor or filter; wherein a phononic structure is etched in the second layer, leaving holes in the second layer; and wherein the etching penetrates through the holes into the second layer, and stopping on the reflective metal layer, leaving a space under the second layer where edges of the first layer etched under the second layer define a length of the integrated backshort.

The present invention provides a process and structure of microfabricated air bridges for planar microwave resonator circuits. In an embodiment, the invention includes depositing a superconducting film on a surface of a base material, where the superconducting film is formed with a compressive stress, where the compressive stress is higher than a critical buckling stress of a defined structure, etching an exposed area of the superconducting film, thereby creating the at least one bridge, etching the base material, thereby forming a gap between the at least one bridge and the base material, depositing the at least one metal line on at least part of the superconducting film and at least part of the base material, where the at least one metal line runs under the bridge.

A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

In various embodiments, superconducting wires incorporate diffusion barriers composed of Nb alloys or NbTa alloys that resist internal diffusion and provide superior mechanical strength to the wires.

Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

A method for fabricating a bridge structure in a quantum mechanical device includes providing a substructure including a substrate having deposited thereon a layer of a first superconducting material divided into a first portion, a second portion and a third portion that are electrically insulated from each other; depositing a sacrificial layer on the substructure; electrically connecting the first portion and the second portion with a strip of a second superconducting material, the second superconducting material being different from the first superconducting material; and removing a portion of the sacrificial layer so as to form a bridge structure over the third portion between the first portion and the second portion, the bridge structure electrically connecting the first portion to the second portion while not electrically connecting the third portion to the first portion and not electrically connecting the third portion to the second portion.

Josephson magnetic memory cells with a semiconductor-based magnetic spin valve are described. An example memory cell includes a first superconducting electrode, a second superconducting electrode, and a semiconductor-based magnetic spin valve arranged between the two superconducting electrodes. The semiconductor-based magnetic spin valve includes a semiconductor layer and a first ferromagnetic insulator arranged near the semiconductor layer, arranged on a first side of the semiconductor layer, configured to provide a fixed magnetization oriented in a first direction. The semiconductor-based magnetic spin valve further includes a second ferromagnetic insulator, arranged on a second side, opposite to the first side, of the semiconductor layer, configured to provide a free magnetization oriented in the first direction or a second direction, opposite to the first direction, in order to control a parameter associated with a flow of current from the first superconducting electrode to the second superconducting electrode through the semiconductor layer.