Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.

An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.

The invention relates to a method of producing a solid-state component, in particular for a quantum component, preferably for a qubit, comprising one or more thin films, the one or more thin films comprising a first material and each said film having a thickness selected between a monolayer and 100 nm and is deposited onto a substrate surface of a substrate, wherein the production process is carried out in a reaction chamber sealed with respect to the ambient atmosphere. Further, the invention relates to a solid-state component, in particular for a quantum component, preferably for a qubit, comprising one or more thin films, one of the one or more thin films comprises a first material with a thickness between a monolayer and 100 nm and is deposited onto a substrate surface of a substrate. In addition, the invention relates to a quantum component comprising such a solid-state component according to the present invention and to an apparatus for producing such a solid-state component according to the present invention.

An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

Provided are a solar cell having a good conversion efficiency in which damage to a p-n junction structure is prevented when an antireflection film is removed, and a method of manufacturing such a solar cell.

An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer, The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.

A method of fabricating a superconducting-semiconducting stack includes cleaning a surface of a substrate, the substrate comprising a group IV element; depositing an insulating buffer layer onto the substrate, the insulating buffer layer comprising the group IV element; depositing a p-doped layer onto the insulating buffer layer; depositing a diffusion barrier onto the p-doped layer; and processing the superconducting-semiconducting stack through dopant activation.

A method for measuring conductance of a material real-time during etching/milling includes providing a fixture having a socket for receiving the material. The socket is attached to a printed circuit board (PCB) mounted on one side of a plate that has at least one opening for providing ion beam access to the material sample. Conductive probes extend from the other side of the PCB to contact and span a target area of the material. A measurement circuit in electrical communication with the probes measures the voltage produced when a current is applied across the material sample to measure changes in electrical properties of the sample over time.

A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.

The present invention relates to the use of gallium beam lithography to form superconductive structures. Generally, the method includes exposing a surface to gallium to form an implanted region and then removing material adjacent to and/or below that implanted region. In particular embodiments, the methods herein provide microstructures and nanostructures in any useful substrate, such as those including niobium, tantalum, tungsten, or titanium.