H10N60/128

Reconfigurable, tunable quantum qubit circuits with internal, nonvolatile memory

A tunable quantum qubit circuit comprising: a plurality of interconnected Josephson tunneling junctions sculpted in-situ on-chip, wherein each Josephson tunneling junction comprises a pair of high temperature superconductors separated by an active region having a controlled charge density; a capacitive-coupled control gate operatively coupled to the Josephson tunneling junctions and configured to simultaneously modulate energy levels of the Josephson tunneling junctions; and independent control gates operatively coupled to the Josephson tunneling junctions, wherein the independent control gates are reconfigurable on-the-fly by an operator.

Layered hybrid quantum architecture for quantum computing applications

A quantum system includes a qubit array comprising a plurality of qubits. A bus resonator is coupled between at least one pair of qubits in the qubit array. A switch is coupled between the at least one qubit pair of qubits.

Tunable Josephson junction oscillator
11430937 · 2022-08-30 · ·

A tunable oscillator including a Josephson junction. In some embodiments, the tunable oscillator includes a first superconducting terminal, a second superconducting terminal, a graphene channel including a portion of a graphene sheet, and a conductive gate. The first superconducting terminal, the second superconducting terminal, and the graphene channel together may form a Josephson junction having an oscillation frequency, and the conductive gate may be configured, upon application of a voltage across the conductive gate and the graphene channel, to modify the oscillation frequency.

Finfet quantum structures utilizing quantum particle tunneling through local depleted well

Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

Method for producing an electronic component with double quantum dots

A process for fabricating an electronic component incorporating double quantum dots and split gates includes providing a substrate surmounted with a stack of a semiconductor layer and of a dielectric layer that is formed above the semiconductor layer. The process also includes forming a mask on the dielectric layer and etching the dielectric layer and the semiconductor layer with the pattern of the mask, so as to form a stack of a semiconductor nanowire and of a dielectric hard mask. Finally, the process includes depositing a gate material on all of the wafer and carrying out a planarization, until the dielectric hard mask is reached, so as to form first and second gates that are electrically insulated from each other on either side of said nanowire.

Photodetector with Superconductor Nanowire Transistor Based on Interlayer Heat Transfer
20210408357 · 2021-12-30 ·

A transistor includes (i) a first wire including a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature and (ii) a second wire including a superconducting component configured to operate in a superconducting state while: a temperature of the superconducting component is below a superconducting threshold temperature and a first input current supplied to the superconducting component is below a current threshold. The semiconducting component is located adjacent to the superconducting component. In response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first input current exceeds the lowered current threshold.

Semiconductor-superconductor hybrid device and its fabrication

A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.

Layered Hybrid Quantum Architecture for Quantum Computing Applications

A quantum system includes a qubit array comprising a plurality of qubits. A bus resonator is coupled between at least one pair of qubits in the qubit array. A switch is coupled between the at least one qubit pair of qubits.

Digital Circuits Comprising Quantum Wire Resonant Tunneling Transistors
20210399198 · 2021-12-23 ·

A digital circuit includes at least one quantum wire resonant tunneling transistor that includes an emitter terminal, a base terminal, a collector terminal, an emitter region in connection with the emitter terminal, a base region in connection with the base terminal, a collector region in connection with the collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region. At least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires.

Reprogrammable quantum processor architecture incorporating quantum error correction

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.