The present disclosure further relates to nanostructures, in particular hybrid nanostructures with patterned growth of various layers for use in nanoscale electronic devices, such as hybrid semiconductor nanostructures with patterned growth and/or deposition of superconducting material for use in quantum devices. The presently disclosed method can be utilized for in-situ manufacturing of nanoscale electronic devices that have not been contaminated by ex-situ processes. One embodiment relates to a method for manufacturing a substrate for growth of crystalline nanostructures, the method comprising the steps of: depositing one or more layers of a crystal growth compatible dielectric material, such as silicon oxide, in a predefined pattern on the surface of a crystal growth compatible substrate to create a predefined etch pattern of said crystal growth compatible material, and selectively etching the substrate surface around said etch pattern to provide at least one under-etched platform which is vertically raised from the etched substrate surface.

A system comprises a substrate having a planar surface; a first magnet configured to apply a first magnetic field parallel to the planar surface; a circuit arranged on the planar surface; and a superconducting quantum interference device, SQUID, operably linked to the circuit. The SQUID comprises a Josephson junction arranged in a superconductive loop. The superconductive loop includes a portion which extends perpendicular to the planar surface and is orientated such that the SQUID is tuneable by the first magnet. By allowing the SQUID to be tuned using a magnetic field which is parallel to the planar surface, a reduction in flux noise may be achieved. Also provided are a method of operating a SQUID, and a SQUID.

A method of fabricating a device, comprising forming portions of electronic circuitry and a shadow wall structure over a substrate, and subsequently depositing a conducting layer over the substrate by angled deposition of a conducting material in at least a first deposition direction at an acute angle relative to the plane of the substrate. The shadow wall structure is arranged to cast a shadow in the deposition, leaving areas where the conducting material is not deposited. The shadow wall structure comprises one or more gaps each shorter than a shadow length of a respective part of the shadow wall structure casting the shadow into the gap, to prevent the conducting material forming in the gaps and to thereby create regions of said upper conducting layer that are electrically isolated from one another. These are arranged to form conducting elements for applying signals to, and/or receiving signals from, the electronic circuitry.

A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material. In a masking phase, a mask is formed on an underlying layer of the device. The mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of the lengths of material. A respective section of two or more of the trenches either (a) narrow down, or (b) are separated by a discontinuity, at a position corresponding to the at least one junction. In a selective area growth phase, material is grown in the set of trenches to form the lengths of material on the underlying layer. The two or more lengths of material are joined at the at least one junction.

A method of fabricating a device, comprising forming portions of electronic circuitry and a shadow wall structure over a substrate, and subsequently depositing a conducting layer over the substrate by angled deposition of a conducting material in at least a first deposition direction at an acute angle relative to the plane of the substrate. The shadow wall structure is arranged to cast a shadow in the deposition, leaving areas where the conducting material is not deposited. The shadow wall structure comprises one or more gaps each shorter than a shadow length of a respective part of the shadow wall structure casting the shadow into the gap, to prevent the conducting material forming in the gaps and to thereby create regions of said upper conducting layer that are electrically isolated from one another. These are arranged to form conducting elements for applying signals to, and/or receiving signals from, the electronic circuitry.

A device including a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions; wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.

An evaporatively cooled device and a system including the same. In some embodiments, the system includes an oligolayer conductive sheet; a superconductor; a tunneling barrier, between the oligolayer conductive sheet and the superconductor; and a bias circuit, configured to apply a bias voltage across the tunneling barrier, the bias voltage being less than a gap voltage of the superconductor and greater than one-half of the gap voltage of the superconductor.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

Techniques that can facilitate high-transparency semiconductor-metal interfaces are provided. In one example, a method can comprise forming a silicon on insulator (SOI) over a wafer. The method can further comprise depositing a metal on the SOI. The method can further comprise forming a structure by dry-etching the metal and dry-etching the SOI. The method can further comprise forming a template over the structure. The method can further comprise etching a portion of the SOI for removal under the metal. The method can further comprise growing a semiconductor where the portion of SOI was removed.