Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm.sup.2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

The method that includes the step of a cleaning a surface of a silicon wafer and forming a sacrificial layer on top of the silicon wafer. The wafer undergoes further processing, wherein the processing includes forming at least one layer directly on top of the sacrificial layer. Immediately prior to the insertion into a dilute refrigeration unit removing a portion of the sacrificial layer by exposing the portion of the sacrificial layer to a solvent.

Devices and/or computer-implemented methods facilitating static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits are provided. In an embodiment, a device can comprise a superconducting bus resonator. The device can further comprise a first superconducting qubit. The device can further comprise a second superconducting qubit, the first superconducting qubit and the second superconducting qubit respectively comprising: a first superconducting pad; a second superconducting pad; a third superconducting pad; a first Josephson Junction coupled to the first superconducting pad and the second superconducting pad; and a second Josephson Junction coupled to the second superconducting pad and the third superconducting pad. The first superconducting pad and the second superconducting pad of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator. The superconducting bus resonator entangles the first superconducting qubit and the second superconducting qubit based on receiving a control signal.

An embodiment of a qubit tuning device includes a first layer configured to generate a magnetic field, the first layer comprising a material exhibiting superconductivity in a cryogenic temperature range. In an embodiment, the qubit tuning device includes a qubit of a quantum processor chip, wherein the first layer is configured to magnetically interact with the qubit such that a first magnetic flux of the first layer causes a first change in a first resonance frequency of the qubit by a first frequency shift value.

Methods, systems and apparatus for implementing a tunable qubit coupler. In one aspect, a device includes: a first data qubit, a second data qubit, and a third qubit that is a tunable qubit coupler arranged to couple to the first data qubit and to couple to the second data qubit such that, during operation of the device, the tunable qubit coupler allows tunable coupling between the first data qubit and the second data qubit.

Josephson junctions (JJ) may replace primary inductance of transformers to realize galvanic coupling between qubits, advantageously reducing size. A long-range symmetric coupler may include a compound JJ (CJJ) positioned at least approximately at a half-way point along the coupler to advantageously provide a higher energy of a first excited state than that of an asymmetric long-range coupler. Quantum processors may include qubits and couplers with a non-stoquastic Hamiltonian to enhance multi-qubit tunneling during annealing. Qubits may include additional shunt capacitances, e.g., to increase overall quality of a total capacitance and improve quantum coherence. A sign and/or magnitude of an effective tunneling amplitude Δ.sub.eff of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).

Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include: a package substrate; a first die coupled to the package substrate; and a second die coupled to the second surface of the package substrate and coupled to the first die; wherein the first die or the second die includes quantum processing circuitry.

The present disclosure discloses a device and a method for fabricating a superconducting circuit including a superconducting qubit. The superconducting circuit comprises a bottom electrode interconnecting a superconducting qubit and a first part of the superconducting circuit. The bottom electrode comprises a bottom electrode of the superconducting qubit and a bottom electrode of the first part of the superconducting circuit. The bottom electrode of the superconducting qubit and the bottom electrode of the first part of the superconducting circuit are formed in a first superconducting layer.

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

A quantum circuit called a “qumon” is provided to cancel unwanted ZZ interaction in a superconducting qubit architecture. The qumon qubit has a high coherence, and a positive anharmonicity that may be tuned to cancel the negative anharmonicity in a coupled qubit, such as a transmon qubit. The qumon has three parallel branches, in which are a shunt capacitor; a Josephson junction having weighted energy level and capacitance; and several Josephson junctions in series. The weight is chosen to provide the desired anharmonicity, and the transverse flux noise and transverse charge noise each decrease in proportion to the number of the Josephson junctions in series. Because unwanted ZZ interactions are canceled, qumon qubits and transmon qubits may be capacitively coupled in an alternating pattern to provide a surface code in which these interactions are canceled in an extensible way.