The present invention discloses a method for manufacturing a phase change memory and a phase change memory. The method comprises: forming a first wafer having a semiconductor-on-insulator structure; forming a memory material layer on the semiconductor-on-insulator structure; and forming a first metal material layer on the memory material layer to form a first semiconductor element.

A filament type non-volatile memory device, includes a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being suitable for having: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, the filament having a low electric resistance, and a highly resistive state, in which the filament is broken, the filament having a high electric resistance. The device further includes a shunt resistance electrically connected in parallel to the active layer, between the first electrode and the second electrode.

Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.

A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.

Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

A switching device includes first and second RF terminals disposed over a substrate, one or more strips of phase change material connected between the first and second RF terminals, a region of thermally insulating material that separates the one or more strips of phase change material from the substrate, and a heater structure comprising one or more heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material. Each of the one or more strips of phase change material includes a first outer face and a second outer face opposite from the first outer face. For each of the one or more strips of phase change material, at least portions of both of the first and second outer faces are disposed against one of the heating elements.

The present disclosure provides a 1T1R resistive random access memory and a manufacturing method thereof, and a device. The 1T1R resistive random access memory includes: a memory cell array composed of multiple 1T1R resistive random access memory cells, each 1T1R resistive random access memory cell including a transistor and a resistance switching device (30). The transistor includes a channel layer (201), a gate layer (204) insulated from the channel layer (201), and a drain layer (203) and a source layer (202) disposed on the channel layer (201), and the drain layer (203) and the source layer (202) are vertically distributed on the channel layer (201). The resistance change device (30) is disposed near the drain layer (203). The disclosure reduces the area of a transistor, thereby significantly improving the memory density of the resistive random access memory.

A semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor substrate; a bottom electrode metal layer and a top electrode metal layer located on the semiconductor substrate; a resistive layer located between the bottom electrode metal layer and the top electrode metal layer, where the transverse width of the resistive layer is greater than the transverse width of the bottom electrode metal layer and/or the top electrode metal layer, and the resistive layer has a variable resistance; an oxygen barrier layer located between the bottom electrode metal layer and the top electrode metal layer, where the oxygen barrier layer is located above the resistive layer; and an oxygen grasping layer located between the bottom electrode metal layer and the top electrode metal layer, where the transverse width of the oxygen grasping layer is less than the transverse width of the resistive layer.

A semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor substrate; a bottom electrode metal layer located in the semiconductor substrate and a top electrode metal layer located on the semiconductor substrate; a resistive layer located between the bottom electrode metal layer and the top electrode metal layer, where the resistive layer has a variable resistance; a first oxygen grasping layer located between the bottom electrode metal layer and the top electrode metal layer, where the first oxygen grasping layer is located above the resistive layer; a second oxygen grasping layer located in the bottom electrode metal layer, where upper surfaces of the semiconductor substrate, the bottom electrode metal layer, and the second oxygen grasping layer are flush, and the resistive layer covers the semiconductor substrate, the bottom electrode metal layer, and the second oxygen grasping layer.

Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.