A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

A memory cell includes a storage element layer, a bottom electrode, a top electrode and a liner layer. The storage element layer has a first surface and a concaved second surface opposite to the first surface. The bottom electrode is disposed on the first surface and connected to the storage element layer. The top electrode is on the concaved second surface and connected to the storage element layer. The liner layer is surrounding the storage element layer and the top electrode.

A memory device is provided that includes a method and structure for forming a resistive memory (RRAM) which has a gradual instead of abrupt change of resistance during programming, rendering it suitable for analog computing. In a first embodiment: One electrode of the inventive RRAM comprises a metal-nitride material (e.g., titanium nitride (TiN)) with gradually changing concentration of a metal composition (e.g., titanium). Different Ti concentrations in the electrode results in different concentration of oxygen vacancy in the corresponding section of the RRAM thereby exhibiting a gradual change of resistance dependent upon an applied voltage. The total conductance of the RRAM is the sum of conductance of each section of the RRAM. In a second embodiment: a RRAM with one electrode having multiple forks of electrodes with different composition concentration and thus different switching behaviors, rendering the inventive RRAM changing conductance gradually instead of abruptly.

A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.

A semiconductor device that includes: first conductive lines; second conductive lines disposed over the first lines to be spaced apart from the first lines; and a selector layer disposed between the first lines and the second lines and including a dielectric material and a dopant doped with a uniform dopant profile.

A phase-change memory device includes a bottom electrode; a stack of alternating electrical conductor layers directly contacting a top surface of the bottom electrode; a metal pillar directly contacting a top surface of the stack; a phase change material element directly contacting a top surface of the metal pillar; and a top electrode on the phase change material element, wherein a lateral dimension of the metal pillar is smaller than that of the stack.

A method is presented for selective deposition on metals using porous low-k materials. The method includes forming alternating layers of a porous dielectric material and a first conductive material, forming a surface aligned monolayer (SAM) over the first conductive material, depositing hydroxamic acid (HA) material over the porous dielectric material, growing an oxide material over the first conductive material, removing the SAM, depositing a dielectric layer adjacent the oxide material, and replacing the oxide material with a second conductive material defining a bottom electrode.

A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.

A resistive random access memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element.

In one example, an electronic device includes a layer of insulator on a substrate extending to a set of device elements. A first set of metal layers having a first thickness lithographically patterned and defined horizontally to the substrate on the layer of insulator. A second set of metal layers with a second thickness having a first portion defined horizontally to the substrate and patterned over and contacting the first set of metal layers, and a second portion defined vertically to the substrate and contacting the first portion and extending vertically through the layer of insulator to at least one device element and contacting the at least one device element with a width of the second thickness thereby creating at least one sub-lithographic film-edge top electrode.