One example includes a method for making a switch. The method includes forming an insulating layer over a substrate. The method also includes forming a resistive heating material over the insulating layer. The method also includes depositing a thermally conductive electrically insulating barrier layer over the heating material. The method also includes forming a phase-change material (PCM) component over the barrier layer spaced apart and proximal to the resistive heating material. The method also includes forming a quench layer proximal to at least one of the resistive heating material and the PCM component. The method further includes forming conductive lines from ends of the PCM component and control lines from ends of the resistive heating material.

The present disclosure relates to a memory device. The memory device includes an access device arranged on or within a substrate and coupled to a word-line and a source line. A plurality of lower interconnects are disposed within a lower dielectric structure over the substrate. A first electrode is coupled to the plurality of lower interconnects. The plurality of lower interconnects couple the access device to the first electrode. A second electrode is over the first electrode. One or more upper interconnects are disposed within an upper dielectric structure laterally surrounding the second electrode. The one or more upper interconnects couple the second electrode to a bit-line. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate varies.

A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.

The disclosed technology provides an electronic device and a fabrication method thereof. An electronic device according to an implementation of the disclosed technology may include: a first interlayer insulating layer formed over a substrate; first and second contact plugs passing through the first interlayer insulating layer to contact the substrate and alternately arranged to cross each other; a variable resistance element formed over the first interlayer insulating layer and coupled to the first contact plug; a second interlayer insulating layer formed over an entire structure including the first interlayer insulating layer; a third contact plug passing through the second interlayer insulating layer so as to be coupled to the variable resistance element, and a fourth contact plug passing through the second interlayer insulating layer so as to be contacted to the second contact plug; and conductive lines coupled to the third contact plug and the fourth contact plug, respectively.

A method for producing a memory device includes depositing a second interlayer insulating film on a substrate, forming contact holes, and depositing a second metal and a nitride film. The second metal and the nitride film are removed to form pillar-shaped nitride layers, and to form lower electrodes surrounding the pillar-shaped nitride layers. The second interlayer insulating film is etched back to expose upper portions of the lower electrodes. The upper portions of the lower electrodes surrounding the pillar-shaped nitride film are removed and a phase change film is deposited to surround the pillar-shaped nitride film and connect with the lower electrodes. The phase change film is etched on upper portions of the pillar-shaped nitride film, and a reset gate insulating film is formed surrounding the phase change film and forming a reset gate having a side wall shape and remaining on the upper portions of the pillar-shaped nitride film.

Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. The diode can include a first diode electrode directly over one of the memory cell electrodes and electrically coupled with the memory cell electrode, and can include a second diode electrode laterally outward of the first diode electrode and not directly over the memory cell. Some embodiments include memory arrays comprising the memory structures, and some embodiments include methods of making the memory structures.

The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.

Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.