Patent classifications
H10N70/257
Tunable hyperbolic metamaterials
An apparatus includes an array of metal nanowires embedded in a matrix of optically tunable material providing a tunable hyperbolic metamaterial, and a control circuit including (i) a current source coupled to first ends of the array of metal nanowires and (ii) a ground voltage coupled to second ends of the array of metal nanowires. The control circuit is configured to modify a state of the optically tunable material utilizing current supplied between the first and second ends of the array of metal nanowires to dynamically reconfigure optical properties of the tunable hyperbolic metamaterial.
Light-activated switching resistor, an optical sensor incorporating a light-activated switching resistor, and methods of using such devices
A switching resistor comprises a dielectric layer disposed between a first electrode layer and a second electrode layer, the switching resistor having a high resistance state and a low resistance state. The switching resistor is responsive to a voltage bias, applied between the first electrode layer and the second electrode layer, wherein the voltage bias exceeds a threshold to switch from the high resistance state to the low resistance state. The switching resistor is sensitive to photo-illumination to reduce said threshold.
TUNABLE HYPERBOLIC METAMATERIALS
An apparatus includes an array of metal nanowires embedded in a matrix of optically tunable material providing a tunable hyperbolic metamaterial, and a control circuit including (i) a current source coupled to first ends of the array of metal nanowires and (ii) a ground voltage coupled to second ends of the array of metal nanowires. The control circuit is configured to modify a state of the optically tunable material utilizing current supplied between the first and second ends of the array of metal nanowires to dynamically reconfigure optical properties of the tunable hyperbolic metamaterial.
ELECTRICALLY ROTATABLE ANTENNAS FORMED FROM AN OPTICALLY TUNABLE MATERIAL
An apparatus includes two or more electrically rotatable antennas providing a reconfigurable metasurface, each of the electrically rotatable antennas including a disk of optically tunable material. The apparatus also includes a control circuit including a plurality of switches each coupled to (i) one of a plurality of electrodes, the plurality of electrodes being arranged proximate different portions of at least one surface of each of the disks of optically tunable material and (ii) to at least one of a current source and a ground voltage. The control circuit is configured to modify states of portions of the optically tunable material in each of the disks of optically tunable material utilizing current supplied between at least two of the plurality of electrodes to adjust reflectivity of the portions of the optically tunable material to dynamically reconfigure respective antenna shape configurations of each of the electrically rotatable antennas.
Optoelectronic memristor devices including one or more solid electrolytes with electrically controllable optical properties
An optoelectronic memristor includes a first electrode, a second electrode, and a solid electrolyte in between that is in electrical communication with the first electrode and the second electrode. The solid electrolyte has an electronic conductivity of about 10.sup.10 Siemens/cm to about 10.sup.4 Siemens/cm at room temperature. The first electrode, and optionally the second electrode, can be optically transparent at a specific wavelength and/or a wavelength range. A direct current (DC) voltage source is employed to apply an electric field across the solid electrolyte, which induces a spatial redistribution of ionic defects in the solid electrolyte. In turn, this causes a change in electrical resistance of the solid electrolyte. The application of the electric field can also cause a change in an optical property of the solid electrolyte at the specific wavelength, and/or at the wavelength range (or a portion thereof).
ReRAM analog PUF using filament location
A semiconductor device is provided. The semiconductor device includes a resistive memory device, and at least a first photodetector and a second photodetector positioned adjacent to the resistive memory device to allow for measurement of the intensity of photon emission from a filament of the resistive memory device.
System on chip (Soc) based on neural processor or microprocessor
System on chips (SoCs) based on a microprocessor or a neural processor (e.g., brain-inspired processor) electrically coupled with electronic memory devices and/or optically coupled with an optical memory device, along with embodiment(s) of a building block (an element) of the microprocessor/neural processor, the electronic memory device and the optical memory device are disclosed. It should be noted that a microprocessor can include a graphical processor. Furthermore, two or more microprocessors/graphical processors/neural processors (or even a network of microprocessors/graphical processors/neural processors) can be coupled with an optical switch to mimic a (biological) cognitive system.
System on chip (SoC) based on neural processor or microprocessor
System on chips (SoCs) based on a microprocessor or a neural processor (e.g., brain-inspired processor) electrically coupled with electronic memory devices and/or optically coupled with an optical memory device, along with embodiment(s) of a building block (an element) of the microprocessor/neural processor, the electronic memory device and the optical memory device are disclosed. It should be noted that a microprocessor can include a graphical processor.
Fast topological switch using strained Weyl semimetals
A method of operating a device includes: (1) providing a film of a semimetal in a first topological phase; and (2) inducing interlayer shear oscillation of the semimetal within the film, wherein the interlayer shear oscillation induces the semimetal to transition to a different, second topological phase.
RRAM CELL STRUCTURE WITH LATERALLY OFFSET BEVA/TEVA
The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.