The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode; a second bit cell with a second top electrode; and a common bottom electrode for both the first bit cell and the second bit cell.

A memory includes a matrix of resistive memory cells and an interfacing device to interface the matrix, the interfacing device including at least a conversion capacitor, an electric source, a first switch and a second switch, the interfacing device being configured to: a) connect the conversion capacitor to the source by the second switch to charge the conversion capacitor, then, b) disconnect the conversion capacitor from the source and connect the conversion capacitor to the matrix to achieve a conversion between, on the one hand, a resistive state of one of the memory cells of the matrix, and, on the other hand, a state of charge of the conversion capacitor.

Integrated circuits including 3D memory structures are disclosed. Air-gaps are purposefully introduced between word lines. The word lines may be horizontal or vertical.

A cross-bar ReRAM comprising a substrate, a plurality of first columns extending parallel to each other on the top surface of the substrate, wherein each of the plurality of the first columns includes a resistive random-access memory (ReRAM) stack comprised of a plurality of layers. A plurality of second columns extending parallel to each other and the plurality of second columns extending perpendicular to the plurality of first columns, wherein the plurality of second columns is located on top of the plurality of first columns, such that the plurality of second columns crosses over the plurality of first columns. A dielectric layer filling in the space between the plurality of first columns and the plurality of second columns, wherein the dielectric layer is in direct contact with a sidewall of each of the plurality layers of the ReRAM stack.

A semiconductor structure may include a vertical field effect transistor, the vertical field effect transistor may include a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory below the vertical field effect transistor. The resistive random access memory may include an epitaxial oxide layer, a top electrode, and a bottom electrode. The top electrode, which may function as the bottom source drain of the vertical field effect transistor, may be in direct contact with the epitaxial channel of the vertical field effect transistor. The epitaxial oxide layer may separate the top electrode from the bottom electrode. The top source drain may be arranged between a dielectric material and the epitaxial channel. The dielectric material may be in direct contact with a top surface of the epitaxial channel. The epitaxial oxide layer may be composed of a rare earth oxide.

A method for programming a phase change memory including a first layer of a phase change material capable of switching between a crystalline and an amorphous state and vice versa, the method including applying a programming current through the first layer so that an evolution of the areal density of this current as a function of time t decreases from a first level, between a first time and a second time, following a first evolution in time respecting, or being close to

[00001]$J_0\left(t\right)=\frac{K}{\sqrt{t}}$

where K is a constant.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.

A cross-bar ReRAM comprising a substrate, a plurality of first columns extending parallel to each other on the top surface of the substrate, wherein each of the plurality of the first columns includes a resistive random-access memory (ReRAM) stack comprised of a plurality of layers. A plurality of second columns extending parallel to each other and the plurality of second columns extending perpendicular to the plurality of first columns, wherein the plurality of second columns is located on top of the plurality of first columns, such that the plurality of second columns crosses over the plurality of first columns. A dielectric layer filling in the space between the plurality of first columns and the plurality of second columns, wherein the dielectric layer is in direct contact with a sidewall of each of the plurality layers of the ReRAM stack.

The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.