A resistive random access memory overcomes the low reliability of the conventional resistive random access memory. The resistive random access memory includes a resistance changing layer and two electrode layers. The two electrode layers are coupled with the resistance changing layer. Each of the two electrode layers includes a doping area containing a heavy element. In such an arrangement, the above deficiency can be overcome.

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.

A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.

The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M.sub.8XY.sub.6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M.sub.8XY.sub.6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell. It may not depend on a gated transistor and a diode, but relies on a non-linear variation characteristic of resistance of its own varied with voltage to achieve a self-gated function, which has a simple structure, easy integration, high density and low cost, capable of suppressing a reading crosstalk phenomenon in a cross array structure; and is also adapted for a planar stacked cross array structure and a vertical cross array structure, achieving 3D storage with a high density.

The present invention provides a neuromorphic memristor device, which includes a resistive switching layer formed on a lower electrode; and an upper electrode formed on the resistive switching layer, in which the resistive switching layer includes an organic metal halide having a perovskite crystal structure.

The present invention is directed to a memory device that includes an array of memory cells. Each of the memory cells includes a memory element connected to a two-terminal selector element. The two-terminal selector element includes a first electrode and a second electrode with a switching layer interposed therebetween. The switching layer includes a plurality of metal-rich clusters embedded in a nominally insulating matrix. One or more conductive paths are formed in the switching layer when an applied voltage to the memory cell exceeds a threshold level. Each of the memory cells may further include an intermediate electrode interposed between the memory element and the two-terminal selector element. The two-terminal selector element may further include a third electrode formed between the first electrode and the switching layer, and a fourth electrode formed between the second electrode and the switching layer.

An electronic synaptic device includes: a lower electrode; an upper electrode; and an active layer provided between the lower electrode and the upper electrode and including a plurality of conductive nanoparticles, wherein the conductive nanoparticles are dispersed in a matrix forming a continuous phase, and the matrix is composed of a protein. The electronic synaptic device has a low switching operation voltage, is capable of implementing a transition phenomenon from a short term potentiation state to a long term potentiation state even with a relatively low voltage, and has high stability; and, therefore, can be preferably applied as a memristive device for implementing neuromorphic computing.

Thin film 1S1R bitcells incorporating a barrier between selector and memory elements. Devices incorporating such bitcells and methods of forming such bitcells are also described. In embodiments, the selector and memory element is each a dielectric material, and advantageously a metal oxide. Between the selector and memory elements is a barrier, which is to reduce intermixing and/or reaction of selector material and memory material. Addition of a barrier layer having suitable material properties into the 1S1R stack may extend the operating lifetime of a bitcell incorporated the stack by resisting intermixing and/or reaction of the selector and memory thin film materials driven by thermal and/or electric field stresses experienced by a bitcell during operation. In embodiments, a barrier layer may include one or more material layers having a composition distinct from the material composition(s) of the selector and memory elements.

Systems, methods, and apparatus are provided for tuning a memristive property of a device. The device (500) includes a layer of a dielectric material (507) disposed over and forming an interface with a layer of an electrically conductive material (506), and a gate electrode (508) disposed over the dielectric material. The dielectric material layer includes at least one ionic species (302) having a high ion mobility. The electrically conductive material is configured such that a potential difference applied to the device can cause the at least one ionic species to migrate reversibly across the interface into or out of the electrically conductive material layer, to modify the resistive state of the electrically conductive material layer.

Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm.sup.2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.