Patent classifications
H01F2027/2809
MULTILAYER COIL COMPONENT
A multilayer coil component includes a multilayer body formed by stacking a plurality of insulating layers in a length direction and that has a built-in coil, and a first outer electrode and a second outer electrode that are electrically connected to the coil. The coil is formed by a plurality of coil conductors stacked in the length direction being electrically connected to each other. The first and second outer electrodes respectively cover at least parts of first and second end surfaces. A stacking direction and a coil axis direction are parallel to the first main surface. A length of a region in which the coil conductors are arranged in the stacking direction is from 85% to 95% of a length of the multilayer body. A distance between coil conductors adjacent to each other in the stacking direction lies in a range from 12 μm to 40 μm.
INDUCTOR
Anchor conductors extending from internal terminal conductors and being in contact with a component body are provided inside the component body. The anchor conductors are provided so as not to be connected to a coil conductor including a circulating portion, and so as not to be exposed on an outer surface of the component body. The anchor conductors are in contact with the component body to thereby enhance fixing force of the internal terminal conductors to the component body.
LOW PASS FILTER, MULTILAYER-TYPE LOW PASS FILTER, AND METHOD OF ADJUSTING FILTER CHARACTERISTIC
A low pass filter includes a first input/output terminal, a second input/output terminal, a signal line, inductors connected in the signal line, and capacitors connected between the signal line and ground. In the signal line, a capacitor is connected in parallel to the inductor that is connected closest to the first input/output terminal, and the inductor and the capacitor define a first parallel resonator.
Power transformer of the symmetric-asymmetric type with a fully-balanced topology
A transformer of the symmetric-asymmetric type includes comprising a primary inductive circuit and a secondary inductive circuit formed in a same plane by respective interleaved and stacked metal tracks. A first crossing region includes a pair of connection plates facing one another, with each connection plate having a rectangular shape that is wider than the metal tracks, and diagonally connected to tracks of the secondary inductive circuit.
Coil component
A laminated coil component 1 includes an element body 2, a coil 8 disposed in the element body 2, and a first external electrode 4 and a second external electrode 5, and at least a part of the coil 8 is disposed in a first region A1 and a second region A2 when seen in a facing direction of the pair of side surfaces 2e and 2f, and the coil 8 is not disposed in a third region A3 and a fourth region A4 when seen in the facing direction of the pair of side surfaces 2e and 2f.
Transimpedance amplifier
A negative feedback inductor and a gate inductor are formed in different wiring layers of a substrate so as to be at least partially overlapped with each other in a plan view. When the lower wiring layer is thinner and the upper wiring layer is thicker, the negative feedback inductor Lc is formed in the lower wiring layer that is thinner.
Multilayer inductor component and method for manufacturing multilayer inductor component
A multilayer inductor component includes an element body that is an insulator and a coil in which a plurality of coil conductor layers that extend along planes in the element body are electrically connected to each other. Also, each of the coil conductor layers includes metal part and glass part, and the glass part include internal glass portion that is entirely included in the metal part.
METHOD OF MANUFACTURING COIL COMPONENT
A method of manufacturing a coil component which includes an element body including magnetic layers stacked in a first direction and having a surface located in the first direction or a second direction reverse to the first direction, a coil and extended wiring in the element body, and an outer electrode at least on the surface. The method includes forming an unbaked coil wiring layer zone by providing a paste-like unbaked coil wiring layer and a paste-like unbaked magnetic layer in the same layer in the direction orthogonal to the first direction on an upper surface of a sheet-like unbaked magnetic layer with respect to the first direction; and forming an unbaked extended wiring layer zone by providing a paste-like unbaked extended wiring layer and a paste-like unbaked magnetic layer in the same layer in the direction orthogonal to the first direction without providing a sheet-like unbaked magnetic layer.
SMALL-SIZE MILLIMETER WAVE ON-CHIP 90-DEGREE 3DB COUPLERS BASED ON SOLENOID STRUCTURES
A 90-degree, 3 dB coupler has an input port, an isolated port, a first output port, and a second output port. A plurality of solenoid structures are arranged in a parallel, spaced relationship. A first group of the interconnects bridge the solenoid structures of a first set that define a first contiguous connection from the input port to the first output port. A second group of interconnects bridge the solenoid structures of a second set that define a second contiguous connection from the isolated port to the second output port. A third group of interconnects bridge the solenoid structures of a third set that define a third contiguous connection from the isolated port to the second output port. The solenoid structures are each unique to a respective one of the first set, second set, and the third set.
SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor chip, an adhesive layer that is formed on the first semiconductor chip, and a second semiconductor chip that is arranged on the first semiconductor chip via the adhesive layer. The first semiconductor chip has a first semiconductor substrate and a first wiring layer. The first wiring layer has a first inductor and a first electrode pad. The first wiring layer is formed on the first semiconductor substrate. The second semiconductor chip has a second wiring layer and a second semiconductor substrate. The second wiring layer is formed on the first wiring layer via the adhesive layer. The second semiconductor substrate is formed on the second wiring layer, and has a first opening. In a plan view, the first electrode pad is formed so as not to overlap with the second semiconductor chip, and a second electrode pad overlaps with the first opening.