A method for manufacturing a carbon-doped silicon single crystal wafer, including steps of: preparing a silicon single crystal wafer not doped with carbon; performing a first RTA treatment on the silicon single crystal wafer in an atmosphere containing compound gas; performing a second RTA treatment at a higher temperature than the first RTA treatment; cooling the silicon single crystal wafer after the second RTA treatment; and performing a third RTA treatment. The crystal wafer is modified to a carbon-doped silicon single crystal wafer, sequentially from a surface thereof: a 3C-SiC single crystal layer; a carbon precipitation layer; a diffusion layer of interstitial carbon and silicon; and a diffusion layer of vacancy and carbon. A carbon-doped silicon single crystal wafer having a surface layer with high carbon concentration and uniform carbon concentration distribution to enable wafer strength enhancement; and a method for manufacturing the carbon-doped silicon single crystal wafer.

A group 13 nitride crystal layer is composed of a group 13 nitride crystal selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof, and the group 13 nitride crystal layer includes an upper surface and bottom surface. The group 13 nitride crystal layer includes high-luminance layers and low-luminance layers being present alternately, and the low-luminance layers have thicknesses of 3 or larger and 10 or smaller provided that 1 is assigned to a thickness of the high-luminance layer, when a cross section of the group 13 nitride crystal layer cut in a direction perpendicular to the upper surface is observed by cathode luminescence.

The present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate; forming an amorphous layer on the substrate, wherein the amorphous layer includes a plurality of patterns to expose part of the substrate; forming a metal nitride layer on the amorphous layer; removing the amorphous layer to form a plurality of cavities between the substrate and the metal nitride layer; removing the substrate to form the semiconductor structure. In the present invention, an amorphous layer is formed on the substrate, and a metal nitride layer is formed on the amorphous layer. The amorphous layer can inhibit slip or dislocation during epitaxial growth, thereby improving the quality of the metal nitride layer and improving the performance of the semiconductor structure, while the metal nitride layer can realize self-supporting.

Systems, apparatuses, and methods are provided for predicting or determining irregular processing parameters during processing of a semiconductor wafer in a semiconductor processing apparatus, such as an etching apparatus. A semiconductor processing apparatus includes a load port that is configured to receive a semiconductor wafer. A process chamber is coupled to the load port, and a fan is configured to selectively vary a flow of fluid in the process chamber. One or more sensors are provided in the process chamber and are configured to sense one or more processing parameters in the process chamber. A controller is coupled to the one or more sensors and to the fan, and the controller is configured to control the fan to vary the flow of fluid in the process chamber based on the sensed one or more processing parameters.

A method of reducing warp imparted to a silicon wafer having a (110) plane orientation and a <111> notch orientation by anisotropic film stress of a multilayer film that is to be formed on a surface of the silicon wafer, that includes forming the multilayer film on a surface of the silicon wafer in an orientation so that a direction in which the warp of the wafer will be greatest coincides with a direction in which Young's modulus of a crystal orientation of the silicon wafer is greatest. Also, a method of reducing warp imparted to a silicon wafer having a (111) plane orientation by isotropic film stress of a multilayer film to be formed on a surface of the silicon wafer, that includes, prior to forming the multilayer film, causing the silicon wafer to have an oxygen concentration of 8.0×10.sup.17 atoms/cm.sup.3 or more (ASTM F-121, 1979).

The present invention relates to technology for fabricating a gallium nitride substrate using an ion implantation process to which a self-separation technique is applied. According to the present invention, a method of fabricating a gallium nitride substrate may include a step of forming a first gallium nitride layer on a substrate, a step of implanting hydrogen ions into the first gallium nitride layer to form a separation layer, a step of grinding the edges of the substrate, the first gallium nitride layer, and the separation layer, a step of forming a second gallium nitride layer on the first gallium nitride layer having a ground edge, and a step of self-separating the second gallium nitride layer from the first gallium nitride layer having a ground edge.

A method for making an article comprising silicon carbide. The method includes producing an article including silicon carbide via additive manufacturing. The method further includes heating via at least one laser beam in a site-selective and locally limited manner a surface of the article so as to cause at least one of ablation and chemical modification of the surface.

The invention discloses a method for cutting a substrate wafer from an indium phosphide crystal, and belongs to the field of semiconductor substrate preparation, comprises the following steps of: 1) orientating, cutting the head and the tail of a crystal bar, adjusting the orientation and trying to cut the crystal bar until a wafer with a required crystal orientation cut, wherein the cutting end face is an orientation end face; 2) multi-wire cutting, on a multi-wire cutting apparatus, dividing a crystal bar parallel to an orientation end face into wafers; 3) cleaning, cleaning the wafer until no residue and no dirt existing on the surface; 4) circle cutting, performing circle cutting on the wafer to cut the desired crystal orientation area. According to the technical scheme, for the indium phosphide crystal bar which is difficult to control in diameter and easy to twinning/ poly in the growth process, a barreling process which may grind and remove a large amount of InP materials is abandoned, the crystal bar is multi-wire cut into a wafer, and then the substrate wafer which is available in the crystal direction close to the standard size is cut from the wafer to the maximum extent, so that the wafer output can be greatly increased, and the material loss and the waste can be reduced.

A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

A method may include thinning a silicon wafer to a particular thickness. The particular thickness may be based on a passband frequency spectrum of an adjustable optical filter. The method may also include covering a surface of the silicon wafer with an optical coating. The optical coating may filter an optical signal and may be based on the passband frequency spectrum. The method may additionally include depositing a plurality of thermal tuning components on the coated silicon wafer. The plurality of thermal tuning components may adjust a passband frequency range of the adjustable optical filter by adjusting a temperature of the coated silicon wafer. The passband frequency range may be within the passband frequency spectrum. The method may include dividing the coated silicon wafer into a plurality of silicon wafer dies. Each silicon wafer die may include multiple thermal tuning components and may be the adjustable optical filter.