Embodiments of the disclosed technology include depositing a passivation layer onto a surface of a wafer that may include a graphene layer. The passivation layer may protect and isolate the graphene layer from electrical and chemical conditions that may damage the graphene layer. As such, the passivation layer may further protect the graphene sensor from being damaged and impaired for its intended use. Additionally, the passivation layer may be patterned to expose select areas of the graphene layer below the passivation layer, thus creating graphene wells and exposing the graphene layer to the appropriate chemicals and solutions.

An etchant for simultaneously etching NiFe and AlN with approximately equal etch rates that comprises phosphoric acid, acetic acid, nitric acid and deionized water. Alternating layers of NiFe and AlN may be used to form a magnetic core of a fluxgate magnetometer in an integrated circuit. The wet etch provides a good etch rate of the alternating layers with good dimensional control and with a good resulting magnetic core profile. The alternating layers of NiFe and AlN may be encapsulated with a stress relief layer. A resist pattern may be used to define the magnetic core geometry. The overetch time of the wet etch may be controlled so that the magnetic core pattern extends at least 1.5 um beyond the base of the magnetic core post etch. The photo mask used to form the resist pattern may also be used to form a stress relief etch pattern.

Provided are a method of manufacturing a thin film transistor, a dehydrogenating apparatus for performing the method, and an organic light emitting display device including a thin film transistor manufactured by the same. A method of manufacturing a thin film transistor includes reducing a content of oxygen in a chamber for performing a dehydrogenation process of an amorphous silicon layer from a first value to a second value, inserting a substrate on which the amorphous silicon layer is formed into the chamber, heating the inside of the chamber to perform the dehydrogenation process on the amorphous silicon layer, and forming a polysilicon layer by crystallizing the amorphous silicon layer using a laser.

Selective deposition methods are described. An exemplary method comprises exposing the substrate comprising a first surface and a second surface to an anchor reactant and selectively depositing the anchor reactant on the first surface as a seed layer, wherein the anchor reactant comprises an ethynyl derivative with a headgroup that selectively targets the first surface.

Method for manufacturing a bonded SOI wafer by bonding a bond wafer and base wafer, each composed of a silicon single crystal, via an insulator film, including the steps: depositing a polycrystalline silicon layer on the base wafer bonding surface side, polishing the polycrystalline silicon layer surface, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the base wafer polycrystalline silicon layer and bond wafer via the insulator film; thinning the bonded bond wafer to form an SOI layer; wherein, in the step of depositing the polycrystalline silicon layer, a wafer having a chemically etched surface as base wafer; chemically etched surface is subjected to primary polishing followed by depositing the polycrystalline silicon layer on surface subjected to the primary polishing, and in the step polishing the polycrystalline silicon layer surface, which is subjected to secondary polishing or secondary and finish polishing.

Methods of producing metal-containing thin films with low impurity contents on a substrate by atomic layer deposition (ALD) are provided. The methods preferably comprise contacting a substrate with alternating and sequential pulses of a metal source chemical, a second source chemical and a deposition enhancing agent. The deposition enhancing agent is preferably selected from the group consisting of hydrocarbons, hydrogen, hydrogen plasma, hydrogen radicals, silanes, germanium compounds, nitrogen compounds, and boron compounds. In some embodiments, the deposition-enhancing agent reacts with halide contaminants in the growing thin film, improving film properties.

A method for fabricating a semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate oxide layer on the first region, the second region, and the third region; and performing an etching process and an infrared treatment process at the same time to completely remove the first gate oxide layer on the second region for exposing the substrate.

Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

A Tunnel Field-Effect Transistor (TFET) includes a source region in a semiconductor substrate, and a drain region in the semiconductor substrate. The source region and the drain region are of opposite conductivity types. The TFET further includes a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack. The gate stack includes a gate dielectric over the semiconductor substrate, and a ferroelectric layer over the gate dielectric.

Embodiments are directed to a method of forming a dielectric region of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric region adjacent a lower portion of the at least one fin, wherein the dielectric region includes a top surface. The method further includes forming a blocking layer on the top surface of the dielectric region, wherein the blocking layer is configured to prevent at least one subsequent FinFET fabrication operation from impacting the top surface of the dielectric region.