Embodiments provide for an optical modulator that includes a first silicon region, a polycrystalline silicon region; a gate oxide region joining the first silicon region to a first side of the polycrystalline region; and a second silicon region formed on a second side of the polycrystalline silicon region opposite to the first side, thereby defining an active region of an optical modulator between the first silicon region, the polycrystalline region, the gate oxide region, and the second silicon region. The polycrystalline silicon region may be between 0 and 60 nanometers thick, and may be formed or patterned to the desired thickness. The second silicon region may be epitaxially grown from the polycrystalline silicon region and patterned into a desired cross sectional shape separately from or in combination with the polycrystalline silicon region.

An organic light emitting diode (OLED) display includes: a substrate; an organic light emitting diode formed on the substrate; a metal oxide layer formed on the substrate and covering the organic light emitting diode; a first inorganic layer formed on the metal oxide layer and covering a relatively larger area than the metal oxide layer; a first organic layer formed on the first inorganic layer and covering a relatively smaller area than the first inorganic layer; and a second inorganic layer formed on the first organic layer, covering a relatively larger area than the first organic layer, and contacting the first inorganic layer at an edge of the second inorganic layer.

The present disclosure relates to a method that includes depositing a first layer onto a substrate, depositing a second layer onto a surface of the first layer, and separating the substrate from the second layer, where the substrate includes a first III-V alloy, the second layer includes second III-V alloy, and the first layer includes a material that includes at least two of a Group 1A element, a Group 2A element, a Group 6A element, and/or a halogen.

A method for manufacturing an array substrate comprises forming a pattern including an active layer, a gate insulating layer and a gate on a base substrate, and forming a pattern including an interlayer dielectric layer, a source, a drain and a pixel electrode through a single patterning process on the base substrate formed with the pattern of the active layer, the gate insulating layer and the gate. An array substrate and a display device are further provided.

The present disclosure provides a DNA-targeting RNA that comprises a targeting sequence and, together with a modifying polypeptide, provides for site-specific modification of a target DNA and/or a polypeptide associated with the target DNA. The present disclosure further provides site-specific modifying polypeptides. The present disclosure further provides methods of site-specific modification of a target DNA and/or a polypeptide associated with the target DNA The present disclosure provides methods of modulating transcription of a target nucleic acid in a target cell, generally involving contacting the target nucleic acid with an enzymatically inactive Cas9 polypeptide and a DNA-targeting RNA. Kits and compositions for carrying out the methods are also provided. The present disclosure provides genetically modified cells that produce Cas9; and Cas9 transgenic non-human multicellular organisms.

A focus ring adjustment assembly of a system for processing workpieces under vacuum, where the focus ring may include a lower side having a first surface portion and a second surface portion, the first surface portion being vertically above the second surface portion. The adjustment assembly may include a pin configured to selectively contact the first surface portion of the focus ring, and an actuator operable to move the pin along the vertical direction between an extended position and a retracted position. The extended position of the pin may be associated with the distal end of the pin contacting the first surface of the focus ring and the focus ring being accessible for removal by a workpiece handling robot from the vacuum process chamber.

A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.

Embodiments of mechanisms for processing a semiconductor wafer are provided. A method for processing a wafer includes providing a wafer process apparatus. The wafer process apparatus includes a chamber and a stage positioned in the chamber for supporting the semiconductor wafer. The method also includes supplying a process gas to the semiconductor wafer via a discharged assembly that is adjacent to the stage. The discharged assembly includes a discharged passage configured without a vertical flow path section.

Disclosed is a method for manufacturing a flexible organic light-emitting diode (OLED) display component which includes steps of: forming a ferromagnetic material layer on a surface of a flexible substrate; and abutting the ferromagnetic material layer against a flat bearing surface, and applying a magnetic pull force directing to the bearing surface on the ferromagnetic material layer. Drawn by the magnetic pull force, the ferromagnetic material layer abuts closely against the flat bearing surface, smoothing out the flexible substrate, and meanwhile fixing the flexible substrate on the bearing surface.

A non-volatile memory device and a method of manufacturing the same are provided. The device includes a substrate including a cell region and a peripheral region, a gate pattern formed over the substrate in the peripheral region, a multilayered structure formed over the gate pattern in the peripheral region, the multilayered structure including interlayer insulating layers and material layers for sacrificial layers, and a capping layer formed between the gate pattern and the multilayered structure in the peripheral region to cover the substrate, the capping layer configured to prevent diffusion of impurities from the material layers for the sacrificial layers into the substrate in the peripheral region.